# US 2017/0288673 A1 · Power efficient voltage level translator circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0288673 A1 - Document ID: US20170288673A1 - Status: Published application - Kind: A1 - Application number: 15/087,812 - Filed: 2016-03-31 - Published: 2017-10-05 - Earliest claimed: 2016-03-31 - Assignees: QUALCOMM Incorporated - Applicants: QUALCOMM Incorporated - Inventors: Rahul Krishnakumar NADKARNI; Anthony CORREALE, JR. - Web page: https://patentgrep.com/patent/US20170288673A1 ## CPC - H03K 19/018521: {of complementary type, e.g. CMOS} - G06F 1/3296: by lowering the supply or operating voltage - H03K 3/012: Modifications of generator to improve response time or to decrease power consumption - H03K 3/35613: {the input circuit having a differential configuration} - H03K 3/356147: {using pass gates} - H03K 19/0016: {by using a control or a clock signal, e.g. in order to apply power supply} - H03K 19/01707: {in asynchronous circuits} - Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE ## Abstract Disclosed systems and methods relate to a power efficient voltage level translator. In a normal mode wherein a first supply voltage of the first voltage domain and a second supply voltage of the second voltage domain are different, the voltage level translator translates an input signal in a first voltage domain to an output signal in a second voltage domain In a bypass mode wherein the first supply voltage and the second supply voltage are substantially the same, a bypass circuit is configured to bypass the voltage level translator and provide the input signal as the output signal in the first voltage domain, thus avoiding delay introduced by the voltage level translator in the bypass mode. Further, a power-down circuit is configured to power-down the voltage level translator in the bypass mode but not in the normal mode. ## Claims ### Claim 1 An apparatus comprising: a voltage level translator configured to translate an input signal in a first voltage domain to an output signal in a second voltage domain, in a normal mode wherein a first supply voltage of the first voltage domain is different from a second supply voltage of the second voltage domain; a bypass circuit configured to bypass the voltage level translator and provide the input signal as the output signal in the first voltage domain, in a bypass mode wherein the first supply voltage and the second supply voltage are substantially the same; and a power-down circuit configured to power-down the voltage level translator in the bypass mode but not in the normal mode. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the power-down circuit comprises a first pull-down transistor configured to gate off a ground connection to the voltage level translator in the bypass mode. ### Claim 3 (depends on 2) The apparatus of claim 2, wherein the power-down circuit further comprises a first pull-up transistor configured to connect an output node of the voltage level translator to the second supply voltage in the bypass mode. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the power-down circuit comprises a second pull-up transistor configured to gate off a connection between the second supply voltage and the voltage level translator in the bypass mode. ### Claim 5 (depends on 4) The apparatus of claim 4, wherein the power-down circuit further comprises a second pull-down transistor configured to connect an output node of the voltage level translator to ground in the bypass mode. ### Claim 6 (depends on 4) The apparatus of claim 4, wherein the power-down circuit further comprises a third pull-down transistor configured to gate off a connection between the voltage level translator and ground in the bypass mode. ### Claim 7 (depends on 6) The apparatus of claim 6, wherein the power-down circuit further comprises a fourth pull-down transistor configured to connect an output node of the voltage level translator to ground in the bypass mode. ### Claim 8 (depends on 6) The apparatus of claim 6, wherein the power-down circuit further comprises a fourth pull-up transistor configured to connect an output node of the voltage level translator to the second supply voltage in the bypass mode. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein the bypass circuit comprises a multiplexer configured to select the input signal in the first voltage domain in the bypass mode and an output of the voltage level translator in the second voltage domain in the normal mode. ### Claim 10 (depends on 1) The apparatus of claim 1, wherein the first voltage domain corresponds to a logic voltage domain comprising logic cells and the second voltage domain corresponds to a memory voltage domain comprising memory cells, wherein the bypass mode corresponds to a turbo mode. ### Claim 11 (depends on 1) The apparatus of claim 1, integrated in a device selected from the group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, server, mobile phone, and a computer. ### Claim 12 A method of voltage level translation, the method comprising: translating, in a voltage level translator, an input signal in a first voltage domain to an output signal in a second voltage domain, in a normal mode wherein a first supply voltage of the first voltage domain is different from a second supply voltage of the second voltage domain; bypassing the voltage level translator and providing the input signal as the output signal in the first voltage domain in a bypass mode, wherein the first supply voltage and the second supply voltage are substantially the same; and powering-down the voltage level translator in the bypass mode but not in the normal mode. ### Claim 13 (depends on 12) The method of claim 12, wherein powering-down the voltage level translator comprises turning off a first pull-down transistor to gate off the voltage level translator from a ground connection in the bypass mode. ### Claim 14 (depends on 13) The method of claim 13, further comprising turning on a first pull-up transistor to connect an output node of the voltage level translator to the second supply voltage in the bypass mode. ### Claim 15 (depends on 12) The method of claim 12, wherein powering-down the voltage level translator comprises turning off a second pull-up transistor configured to gate off a connection between the second supply voltage and the voltage level translator in the bypass mode. ### Claim 16 (depends on 15) The method of claim 15, further comprising turning on a second pull-down transistor to connect an output node of the voltage level translator to ground in the bypass mode. ### Claim 17 (depends on 15) The method of claim 15, further comprising turning off a third pull-down transistor to gate off a connection between the voltage level translator and ground in the bypass mode. ### Claim 18 (depends on 17) The method of claim 17, further comprising turning on a fourth pull-down transistor to connect an output node of the voltage level translator to ground in the bypass mode. ### Claim 19 (depends on 17) The method of claim 17, further comprising turning on a fourth pull-up transistor to connect an output node of the voltage level translator to the second supply voltage in the bypass mode. ### Claim 20 (depends on 12) The method of claim 12, comprising selecting the input signal in the first voltage domain in the bypass mode and an output of the voltage level translator in the second voltage domain in the normal mode. ### Claim 21 (depends on 12) The method of claim 12, wherein the first voltage domain corresponds to a logic voltage domain comprising logic cells and the second voltage domain corresponds to a memory voltage domain comprising memory cells, wherein the bypass mode corresponds to a turbo mode. ### Claim 22 An apparatus comprising: means for translating an input signal in a first voltage domain to an output signal in a second voltage domain, in a normal mode wherein a first supply voltage of the first voltage domain is different from a second supply voltage of the second voltage domain; means for bypassing the means for translating, and providing the output signal in the first voltage domain in a bypass mode, wherein the first supply voltage and the second supply voltage are substantially the same; and means for powering-down the voltage level translator in the bypass mode but not in the normal mode. ### Claim 23 (depends on 22) The apparatus of claim 22, wherein the means for powering-down the voltage level translator comprises means for gating off the voltage level translator from a ground connection in the bypass mode. ### Claim 24 (depends on 23) The apparatus of claim 23, further comprising means for connecting an output node of the voltage level translator to the second supply voltage in the bypass mode. ### Claim 25 (depends on 22) The apparatus of claim 22, wherein the means for powering-down the voltage level translator comprises means for gating off a connection between the second supply voltage and the voltage level translator in the bypass mode. ### Claim 26 (depends on 25) The apparatus of claim 25, further comprising means for connecting an output node of the voltage level translator to ground in the bypass mode. ### Claim 27 (depends on 25) The apparatus of claim 25, further comprising means for gating off a connection between the voltage level translator and ground in the bypass mode. ### Claim 28 (depends on 27) The apparatus of claim 27, further comprising means for connecting an output node of the voltage level translator to ground in the bypass mode. ### Claim 29 (depends on 27) The apparatus of claim 27, further comprising means for connecting an output node of the voltage level translator to the second supply voltage in the bypass mode. ### Claim 30 (depends on 22) The apparatus of claim 22, further comprising means for selecting the input signal in the first voltage domain in the bypass mode and an output of the voltage level translator in the second voltage domain in the normal mode.