# US 2017/0288671 A1 · Pipelined interconnect circuitry with double data rate interconnections > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0288671 A1 - Document ID: US20170288671A1 - Status: Published application - Kind: A1 - Application number: 15/630,436 - Filed: 2017-06-22 - Published: 2017-10-05 - Earliest claimed: 2014-08-20 - Assignees: Altera Corporation - Applicants: Altera Corporation - Inventors: David Lewis; Herman Henry Schmit; Carl Ebeling - Web page: https://patentgrep.com/patent/US20170288671A1 ## CPC - H03K 19/017581: {programmable} - H03K 19/017509: {Interface arrangements} - H03K 19/018521: {of complementary type, e.g. CMOS} - H03K 19/1737: {using multiplexers (H03K19/1738 takes precedence)} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract An integrated circuit may have pipelined interconnects that are configurable to operate in registered single data rate mode, registered double data rate mode, or in combinational mode. The pipelined interconnect may include routing multiplexers for selecting incoming signals, circuitry for serialization and de-serialization, and memory elements that are configurable to store one or two signals per clock period. Operating the pipeline interconnects in double data rate mode may provide a trade-off between reducing the number of physical wires that are required to implement a design at a constant bandwidth or increasing the bandwidth while keeping the number of physical wires constant. ## Claims ### Claim 1 An integrated circuit, comprising: a selection circuit configured to receive first and second signals; control circuitry coupled to the selection circuit and configured to receive a clock signal and to control the selection circuit to generate a double data rate signal based on the clock signal by serializing the first and second signals; and a storage element coupled to the selection circuit and configured to store the double data rate signal. ### Claim 2 (depends on 1) The integrated circuit defined in claim 1, further comprising: a driver circuit having an input and an output; and an additional selection circuit interposed between the input of the driver circuit and the storage element and configured to selectively provide the stored double data rate signal to the driver circuit. ### Claim 3 (depends on 2) The integrated circuit defined in claim 2, wherein the additional selection circuit includes an input terminal that is directly connected to the selection circuit. ### Claim 4 (depends on 3) The integrated circuit defined in claim 3, wherein the control circuitry is configured to control the additional selection circuit to bypass the storage element and provide data signals received at the input terminal of the additional selection circuit to the input of the driver circuit. ### Claim 5 (depends on 1) The integrated circuit defined in claim 1, further comprising: an additional storage element coupled to the selection circuit and configured to receive the double data rate signal and de-serialize the received double data rate signal. ### Claim 6 (depends on 5) The integrated circuit defined in claim 5, wherein the additional storage element is configured to store only a portion of the received double data rate signal during a clock period of the clock signal and wherein the portion of the received double data rate signal comprises the first signal. ### Claim 7 (depends on 1) The integrated circuit defined in claim 1, wherein the storage element is configured to store a first portion of the double data rate signal that includes the first signal during a first portion of a clock period of the clock signal and the storage element is configured to store a second portion of the double data rate signal that includes the second signal during a second portion of the clock period of the clock signal. ### Claim 8 (depends on 1) The integrated circuit defined in claim 1, wherein the control circuitry controls the selection circuit to select the first signal during a first portion of a clock period of the clock signal and that selects the second signal during a second portion of the clock period of the clock signal. ### Claim 9 (depends on 1) The integrated circuit defined in claim 1, wherein the selection circuit is configured to generate the double data rate signal in a first mode of operation and to generate a single data rate signal in a second mode of operation. ### Claim 10 (depends on 9) The integrated circuit defined in claim 9, wherein the control circuitry is coupled to the storage element, wherein, in the first mode of operation, the control circuitry configures the storage element to store the first and second signals during respective portions of a given clock period in the clock signal, and wherein, in the second mode of operation, the control circuitry configures the storage element to store a signal selected from one of the first and second signals during an additional clock period in the clock signal. ### Claim 11 Interconnect circuitry, comprising: a multiplexer that receives a plurality of routing signals and selects a routing signal from the plurality of routing signals; a mode selection circuit that receives a clock signal and that produces a mode selection signal based on the clock signal; and a pipeline circuit that receives the mode selection signal from the mode selection circuit and that receives the selected routing signal from the multiplexer, wherein the pipeline circuit operates in a selected one of a double data rate mode and a storage bypass mode based on the mode selection signal. ### Claim 12 (depends on 11) The interconnect circuitry defined in claim 11, wherein the pipeline circuit further comprises: a memory element that operates in double data rate mode, wherein the memory element stores a first portion of the selected routing signal during a first portion of a period of the clock signal and a second portion of the selected routing signal during a second portion of the period of the clock signal. ### Claim 13 (depends on 11) The interconnect circuitry defined in claim 11, wherein the pipeline circuit further comprises: a deserialization circuit that receives the selected routing signal and produces first and second portions of the selected routing signal on first and second outputs. ### Claim 14 (depends on 13) The interconnect circuitry defined in claim 13, wherein the deserialization circuit further comprises: a first memory element that stores the first portion of the selected routing signal during a first portion of a period of the clock signal; and a second memory element that stores the second portion of the selected routing signal during a second portion of the period of the clock signal. ### Claim 15 (depends on 11) The interconnect circuitry defined in claim 11, further comprising: an additional multiplexer that receives an additional plurality of routing signals and selects an additional routing signal among the additional plurality of routing signals; and a serialization circuit that is coupled to the pipeline circuit and that receives the selected routing signal from the multiplexer and the selected additional routing signal from the additional multiplexer, wherein the serialization circuit sends a serialized routing signal to the pipeline circuit by sending the selected routing signal during a first portion of a period of the clock signal and the selected additional routing signal during a second portion of a period of the clock signal. ### Claim 16 (depends on 11) The interconnect circuitry defined in claim 11, wherein the pipeline circuit additionally operates in single data rate mode based on the mode selection signal. ### Claim 17 An integrated circuit, comprising: interconnect circuitry configured to receive first and second signals and to generate a third signal based on the first and second signals; and control circuitry coupled to the interconnect circuitry and configured to provide control signals that operate the interconnect circuitry as a double data rate interconnect circuit in a first mode, a single data rate interconnect circuit in a second mode, and a storage bypass interconnect circuit in a third mode. ### Claim 18 (depends on 17) The integrated circuit defined in claim 17, wherein the interconnect circuitry includes a multiplexer configured to receive the first signal and the second signal and to generate an output signal based on the first and second signal. ### Claim 19 (depends on 18) The integrated circuit defined in claim 18, wherein the interconnect circuitry includes an additional multiplexer directly coupled to the multiplexer via a wired path and coupled to the multiplexer through a pipeline element. ### Claim 20 (depends on 19) The integrated circuit defined in claim 19, wherein the storage bypass interconnect circuit in the third mode generates the third signal by bypassing the pipeline element.