# US 2017/0288670 A1 · Semiconductor Device, Electronic Component, and Electronic Device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0288670 A1 - Document ID: US20170288670A1 - Status: Published application - Kind: A1 - Application number: 15/471,516 - Filed: 2017-03-28 - Published: 2017-10-05 - Earliest claimed: 2016-04-01 - Assignees: Semiconductor Energy Laboratory Co., Ltd. - Applicants: Semiconductor Energy Laboratory Co., Ltd. - Inventors: Munehiro KOZUMA; Yoshiyuki KUROKAWA - Web page: https://patentgrep.com/patent/US20170288670A1 ## CPC - H03K 19/0008: {Arrangements for reducing power consumption} - H03K 19/17728: Reconfigurable logic blocks, e.g. lookup tables - H03K 19/17744: {for input/output signals} - H03K 19/1776: for memories - H03K 21/026: {comprising logic circuits} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Skew of a multi-context PLD in context switch is reduced to achieve low power consumption. The frequency of a clock signal is switched in context switch operation in accordance with circuit operation to secure time required for context switch. By returning the frequency of the clock signal to the original frequency after executing the context switch, the PLD can maintain high-speed processing and perform the context switch accurately and safely. The time required for the context switch mainly depends on a hardware structure (circuit layout including a parasitic component). Thus, the reliability in the context switch can be improved when time that is equal to or longer than the longest time required for circuit change is secured. ## Claims ### Claim 1 A semiconductor device comprising: a context controller; a clock generation circuit; a programmable circuit; and a switch circuit, wherein the programmable circuit includes a programmable logic element, wherein the context controller is configured to detect context switch and generate a switch signal in accordance with the context switch, wherein the clock generation circuit is configured to generate a second clock signal, wherein a frequency of the second clock signal is lower than a frequency of a first clock signal, and wherein the switch circuit is configured to supply the first clock signal or the second clock signal to the programmable logic element in response to the switch signal. ### Claim 2 (depends on 1) The semiconductor device according to claim 1, wherein the context controller detects switching of a context control signal. ### Claim 3 (depends on 1) The semiconductor device according to claim 1, wherein the second clock signal is generated in a period during which the context switch is performed. ### Claim 4 (depends on 1) The semiconductor device according to claim 1, wherein the clock generation circuit comprises a frequency divider generating the second clock signal. ### Claim 5 (depends on 1) An electronic component comprising: the semiconductor device according to claim 1; and a lead electrically connected to the semiconductor device. ### Claim 6 (depends on 5) An electronic device comprising: the electronic component according to claim 5; and at least one of a display device, a touch panel, a microphone, a speaker, an operation key, and a housing. ### Claim 7 A semiconductor device comprising: a context controller; a clock generation circuit; a programmable circuit; and a switch circuit, wherein the programmable circuit includes a programmable logic element, wherein the context controller includes a detection circuit, a signal generation circuit, and a determination circuit, wherein the detection circuit is configured to detect context switch, wherein the signal generation circuit is configured to generate a context signal in accordance with the context switch, wherein the determination circuit is configured to generate a switch signal in accordance with the context switch, wherein the clock generation circuit is configured to generate a second clock signal, wherein a frequency of the second clock signal is lower than a frequency of a first clock signal, and wherein the switch circuit is configured to supply the first clock signal or the second clock signal to the programmable logic element in response to the switch signal. ### Claim 8 (depends on 7) The semiconductor device according to claim 7, wherein the detection circuit detects switching of a context control signal. ### Claim 9 (depends on 7) The semiconductor device according to claim 7, wherein the second clock signal is generated in a period during which the context switch is performed. ### Claim 10 (depends on 7) The semiconductor device according to claim 7, wherein the clock generation circuit comprises a frequency divider generating the second clock signal. ### Claim 11 (depends on 7) An electronic component comprising: the semiconductor device according to claim 7; and a lead electrically connected to the semiconductor device. ### Claim 12 (depends on 11) An electronic device comprising: the electronic component according to claim 11; and at least one of a display device, a touch panel, a microphone, a speaker, an operation key, and a housing. ### Claim 13 A semiconductor device comprising: a context controller; a clock generation circuit; a programmable circuit; and a switch circuit, wherein the programmable circuit includes a programmable logic element, wherein the programmable logic element includes a flip-flop and a backup circuit capable of retaining data retained in the flip-flop, wherein the context controller includes a detection circuit, a signal generation circuit, and a determination circuit, wherein the detection circuit is configured to detect context switch, wherein the signal generation circuit is configured to generate a context signal in accordance with the context switch, wherein the determination circuit is configured to generate a switch signal in accordance with the context switch, wherein the clock generation circuit is configured to generate a second clock signal and a third clock signal, wherein a frequency of the second clock signal and a frequency of the third clock signal are lower than a frequency of a first clock signal, wherein the clock generation circuit outputs the second clock signal in a period during which data is input from the flip-flop to the backup circuit and outputs the third clock signal in a period during which the data is input from the backup circuit to the flip-flop, and wherein the switch circuit is configured to supply the first clock signal, the second clock signal, or the third clock signal to the programmable logic element in response to the switch signal. ### Claim 14 (depends on 13) The semiconductor device according to claim 13, wherein the detection circuit detects switching of a context control signal. ### Claim 15 (depends on 13) The semiconductor device according to claim 13, wherein the clock generation circuit comprises a first frequency divider generating the second clock signal and a second frequency divider generating the third clock signal. ### Claim 16 (depends on 15) The semiconductor device according to claim 15, wherein the clock generation circuit further comprises a second switch circuit, and wherein the second switch circuit is configured to switch and output the second clock signal or the third clock signal. ### Claim 17 (depends on 13) The semiconductor device according to claim 13, wherein the backup circuit includes a first transistor and a second transistor, wherein the first transistor includes an oxide semiconductor in a semiconductor layer serving as a channel formation region, wherein one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor, and wherein the first transistor is capable of holding charge in the gate of the second transistor by turning off the first transistor. ### Claim 18 (depends on 13) An electronic component comprising: the semiconductor device according to claim 13; and a lead electrically connected to the semiconductor device. ### Claim 19 (depends on 18) An electronic device comprising: the electronic component according to claim 18; and at least one of a display device, a touch panel, a microphone, a speaker, an operation key, and a housing.