# US 2017/0288669 A1 · Calibration circuit and calibration apparatus including the same

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- Number: US 2017/0288669 A1
- Document ID: US20170288669A1
- Status: Published application
- Kind: A1
- Application number: 15/626,648
- Filed: 2017-06-19
- Published: 2017-10-05
- Earliest claimed: 2014-10-28
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Oung Sic CHO; Jong Hoon OH
- Web page: https://patentgrep.com/patent/US20170288669A1

## CPC

- H03K 19/0005: {Modifications of input or output impedance}
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A calibration circuit sharing a resistor for impedance matching includes a command decoder configured to receive a command signal and decode the command signal into a calibration enable signal; a selector configured to select one of the calibration enable signal and a start signal according to a select signal, and provide a driving signal; and a calibration driver configured to perform an impedance matching operation in response to the driving signal, and generate a completion signal when performance is completed, wherein the start signal corresponds to a completion signal provided from another calibration circuit which shares the resistor for the impedance matching.

## Claims

### Claim 1

A calibration circuit sharing a resistor for impedance matching, comprising:
a command decoder configured to receive a command signal and decode the command signal into a calibration enable signal;
a selector configured to select one of the calibration enable signal and a start signal according to a select signal, and provide a driving signal; and
a calibration driver configured to perform an impedance matching operation in response to the driving signal, and generate a completion signal when performance is completed,
wherein the start signal corresponds to a completion signal provided from another calibration circuit which shares the resistor for the impedance matching.

### Claim 2 (depends on 1)

The calibration circuit according to claim 1, wherein the command decoder selectively provides the calibration enable signal to the selector according to a chip select signal.

### Claim 3 (depends on 1)

The calibration circuit according to claim 1, further comprising:
a register configured to receive a mode signal indicating an order of a corresponding calibration circuit among calibration circuits which share the resistor for the impedance matching, and provide the select signal.

### Claim 4 (depends on 1)

The calibration circuit according to claim 1, wherein the calibration driver comprises a completion signal generation unit configured to generate the completion signal when a preset time has passed after the impedance matching operation is started in response to the driving signal.

### Claim 5 (depends on 1)

The calibration circuit according to claim 1, wherein the calibration driver comprises a completion signal generation unit configured to generate the completion signal when a matching code generated according to the impedance matching operation is not changed for a predetermined time.

### Claim 6

A calibration apparatus comprising:
a first calibration circuit configured to perform an impedance matching operation according to a resistor for impedance matching in response to a first calibration enable signal generated by decoding a command signal, and generate a completion signal when performance is completed; and
a second calibration circuit configured to share the resistor for the impedance matching with the first calibration circuit, and perform an impedance matching operation according to the completion signal.

### Claim 7 (depends on 6)

The calibration apparatus according to claim 6, wherein the first calibration circuit is formed on a first die, the second calibration circuit is formed on a second die, and the calibration apparatus is formed on one substrate.

### Claim 8 (depends on 7)

The calibration apparatus according to claim 7, wherein the second calibration circuit comprises:
a command decoder configured to receive the command signal and generate a second calibration enable signal;
a selector configured to select the completion signal between the completion signal and the second calibration enable signal according to a select signal, and provide a driving signal; and
a calibration driver configured to perform the impedance matching operation according to the driving signal.

### Claim 9 (depends on 8)

The calibration apparatus according to claim 8, wherein the command decoder selectively generates the second calibration enable signal by receiving a chip select signal.

### Claim 10 (depends on 8)

The calibration apparatus according to claim 8, further comprising:
a register configured to receive a mode signal indicating an order of the second calibration circuit among a plurality of calibration circuits which share the resistor for the impedance matching and provide the select signal.

### Claim 11 (depends on 8)

The calibration apparatus according to claim 8, wherein a voltage corresponding to a select signal for indicating an order of the second calibration circuit among a plurality of calibration circuits which share the resistor for the impedance matching is received through a pad.

### Claim 12 (depends on 6)

The calibration apparatus according to claim 6, wherein the first calibration circuit comprises a completion signal generation unit configured to generate the completion signal when a preset time has passed after the impedance matching operation is started.

### Claim 13 (depends on 6)

The calibration apparatus according to claim 6, wherein the first calibration circuit comprises a completion signal generation unit configured to generate the completion signal when a matching code generated according to the impedance matching operation is not changed for a predetermined time.

### Claim 14

A calibration circuit, comprising:
a selector configured to select a calibration enable signal or a start signal in response to a select signal to provide a driving signal;
a calibration driver configured to perform an impedance matching operation according to the driving signal and generate a completion signal,
wherein the calibration driver performs the impedance matching operation by comparing a value received from a resistor for impedance matching to a reference value for generating a matching code.

### Claim 15 (depends on 14)

The calibration circuit according to claim 14, wherein the calibration driver comprises:
an impedance comparison unit configured to receive the value of the resistor for the impedance matching and compare the value with the reference value for the generating of the matching code.

### Claim 16 (depends on 15)

The calibration circuit according to claim 15, wherein the calibration driver comprises:
a matching code generation unit configured to generate a matching code according to a comparison signal.

### Claim 17 (depends on 16)

The calibration circuit according to claim 16, wherein the calibration driver comprises:
a completion signal generation unit configured to generate a completion signal when the impedance matching is completed.

### Claim 18 (depends on 17)

The calibration circuit according to claim 17, wherein the completion signal is generated when the matching code is not changed for a predetermined time.

### Claim 19 (depends on 14)

The calibration circuit according to claim 14, wherein the impedance matching is performed repeatedly with a constant cycle after being initiated in response to the driving signal.

### Claim 20 (depends on 16)

The calibration circuit according to claim 16, wherein the impedance comparison unit provides the comparison signal to the matching code generation unit.
