# US 2017/0288665 A1 · Method and apparatus for edge equalization for high speed drivers > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0288665 A1 - Document ID: US20170288665A1 - Status: Published application - Kind: A1 - Application number: 15/280,059 - Filed: 2016-09-29 - Published: 2017-10-05 - Earliest claimed: 2016-04-04 - Assignees: Mediatek Inc. - Applicants: MediaTek Inc. - Inventors: Tamer Ali - Web page: https://patentgrep.com/patent/US20170288665A1 ## CPC - H03K 17/6872: {using complementary field-effect transistors} - H03K 5/134: with field-effect transistors - H04B 3/04: Control of transmission; Equalising - H04L 25/02: Details {; arrangements for supplying electrical power along data transmission lines (systems for transmitting signals via power distribution lines H04B3/54)} - H04L 25/03878: {Line equalisers; line build-out devices} - H03K 2005/00195: {using FET's} - H04B 1/04: Circuits - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H04B: TRANSMISSION - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract A line driver for signal equalization is described. The line driver may comprise an equalization driver and a gating circuit. The gating circuit may be configured to gate the equalization driver between a first transition and a second transition, such as between a rising edge and a falling edge. The gating circuit may comprise one or more delay elements, such as one or more inverters, configured to generate the second transition in response to receiving the first transition, where the second transition is delayed with respect to the first transition. Such line driver may be used to signals having high data rates to transmission lines, such as cables or metal connection on printed circuit boards. ## Claims ### Claim 1 A line driver comprising: a first driver connected to a transmission line and configured to drive the transmission line with a first output signal in response to receiving an input signal; a second driver connected to the transmission line and configured to drive the transmission line with a second output signal; and a gating circuit configured to activate the second driver for a period of time in response to receiving the input signal, wherein the second driver is configured to drive the transmission line for the period of time. ### Claim 2 (depends on 1) The line driver of claim 1, wherein when the input signal exhibits a first transition, the gating circuit is configured to generate a second transition, the second transition being delayed with respect to the first transition, and wherein the period of time is from the first transition to the second transition. ### Claim 3 (depends on 2) The line driver of claim 2, wherein the first transition comprises a rising edge and the second transition comprises a falling edge. ### Claim 4 (depends on 1) The line driver of claim 1, wherein the gating circuit comprises at least one delay element. ### Claim 5 (depends on 1) The line driver of claim 1, wherein the period of time is between 10 ps and 30 ps. ### Claim 6 (depends on 1) The line driver of claim 1, wherein the first output signal varies at a first maximum frequency and the second output signal varies at a second maximum frequency, and wherein the second maximum frequency is greater than the first maximum frequency. ### Claim 7 (depends on 1) The line driver of claim 1, wherein the second driver comprises at least four transistors comprising a first plurality of transistors having a first type of conductivity and a second plurality of transistors having a second type of conductivity, and wherein the at least four transistors are connected in series. ### Claim 8 (depends on 7) The line driver of claim 7, wherein at least one of the first plurality of transistors having the first type of conductivity is connected to a first delay element and at least one of the second plurality of transistors having the second type of conductivity is connected to a second delay element. ### Claim 9 (depends on 7) The line driver of claim 7, wherein the first plurality of transistors having the first type of conductivity are NMOS transistors and the second plurality of transistors having the second type of conductivity are PMOS transistors. ### Claim 10 (depends on 1) The line driver of claim 1, wherein the second driver is differential. ### Claim 11 (depends on 1) The line driver of claim 1, wherein the transmission line comprises a metal connection on a printed circuit board. ### Claim 12 (depends on 1) The line driver of claim 1, wherein the first driver comprises a voltage mode driver. ### Claim 13 A method for driving a transmission line, the method comprising: using a first driver, driving the transmission line with a first output signal in response to receiving an input signal; activating, using a gating circuit, a second driver for a period of time in response to receiving the input signal; and driving the transmission line with a second output signal using the second driver for the period of time. ### Claim 14 (depends on 13) The method of claim 13, wherein the period of time is less than a periodicity of the input signal. ### Claim 15 (depends on 13) The method of claim 13, wherein activating the second driver comprises generating, with the gating circuit, a second transition when the input signal exhibits a first transition, wherein the second transition is delayed with respect to the first transition, and wherein the period of time is from the first transition to the second transition. ### Claim 16 (depends on 15) The line driver of claim 15, wherein the first transition comprises a rising edge and the second transition comprises a falling edge. ### Claim 17 (depends on 13) The method of claim 13, wherein the period of time is between 10 ps and 30 ps. ### Claim 18 (depends on 13) The method of claim 13, wherein activating the second driver comprises activating one or more transistors. ### Claim 19 (depends on 13) The method of claim 13, wherein the first output signal varies at a first maximum frequency and the second output signal varies at a second maximum frequency, and wherein the second maximum frequency is greater than the first maximum frequency. ### Claim 20 (depends on 13) The method of claim 13, wherein the second signal is differential.