# US 2017/0288658 A1 · Resistor array, output buffer, and manufacturing method for semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0288658 A1 - Document ID: US20170288658A1 - Status: Published application - Kind: A1 - Application number: 15/474,168 - Filed: 2017-03-30 - Published: 2017-10-05 - Earliest claimed: 2016-03-31 - Assignees: Lapis Semiconductor Co., Ltd. - Applicants: LAPIS Semiconductor Co., Ltd. - Inventors: Seiichiro SASAKI - Web page: https://patentgrep.com/patent/US20170288658A1 ## CPC - H03K 17/16: Modifications for eliminating interference voltages or currents - H03F 1/56: Modifications of input or output impedances, not otherwise provided for - H03F 3/211: {using a combination of several amplifiers (H03F3/60 takes precedence)} - H03K 19/0005: {Modifications of input or output impedance} - H10D 1/47: Resistors having no potential barriers - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) - H03F: AMPLIFIERS - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A resistor array made of a semiconductor includes a plurality of resistor groups and a common line that electrically connects the M-th resistors of the plurality of resistor groups. Each resistor group includes first to M-th resistors connected in series, M being an integer of 2 or greater, and at least one short-circuit line, each short-circuiting at least one, but not all, of the M resistors. ## Claims ### Claim 1 A resistor array made of a semiconductor, comprising: a plurality of resistor groups, each including first to M-th resistors connected in series, M being an integer of 2 or greater, and at least one short-circuit line, each short-circuiting at least one, but not all, of the M resistors; and a common line that electrically connects the M-th resistors of the plurality of resistor groups. ### Claim 2 (depends on 1) The resistor array according to claim 1, wherein the at least one short-circuit line includes a plurality of short-circuit lines. ### Claim 3 (depends on 1) The resistor array according to claim 1, wherein the resistors in each resistor group have resistance values different from one other. ### Claim 4 (depends on 1) A manufacturing method of a semiconductor device having a resistor array according to claim 1, comprising: obtaining target information indicating the at least one resistor for each short-circuit line in each resistor group; and manufacturing the semiconductor device based on the target information. ### Claim 5 (depends on 4) The manufacturing method of a semiconductor device according to claim 4, wherein the obtaining target information includes: manufacturing a tester semiconductor device including a plurality of tester resistor groups respectively corresponding to the plurality of resistor groups of the semiconductor device, each tester resistor group including first to M-th tester resistors connected in series that respectively correspond to the first to M-th resistors of the corresponding resistor group of the semiconductor device, and at least one short-circuit line, each short-circuiting at least one, but not all, of the M tester resistors, and a common line that electrically connects the M-th tester resistors of the plurality of tester resistor groups, measuring a resistance value of at least one test resister of the plurality of tester resistor groups, and generating the target information using the measured resistance value. ### Claim 6 (depends on 5) The manufacturing method of a semiconductor device according to claim 5, wherein the obtaining target information further includes calculating a resistance value of another resistor of the plurality of tester resistor groups, using the measured resistance value, and the target information is generated using the measured resistance value and the calculated resistance value. ### Claim 7 (depends on 4) The manufacturing method of a semiconductor device according to claim 4, wherein the resistors in each resistor group are manufactured to have resistance values different from one other. ### Claim 8 An output buffer for receiving an input signal and outputting an output signal through an external terminal, comprising: an output resistor circuit including a plurality of resistor groups, each including first to M-th resistors connected in series, M being an integer of 2 or greater, and at least one short-circuit line, each short-circuiting at least one, but not all, of the M resistors; and a common line that electrically connects the M-th resistors of the plurality of resistor groups; and a driver circuit including a plurality of drivers respectively corresponding to the plurality of resistor groups, each driver supplying an amplified signal, obtained by amplifying the input signal, to the corresponding one of the plurality of resistor groups. ### Claim 9 (depends on 8) The output buffer according to claim 8, wherein the at least one short-circuit line includes a plurality of short-circuit lines. ### Claim 10 (depends on 8) The output buffer according to claim 8, wherein the M resistors in each resistor group have resistance values different from one other. ### Claim 11 An output buffer for receiving an input signal and outputting an output signal through an external terminal, comprising: an output resistor circuit including first to n-th resistor circuits, and a common line that electrically connects one end of each of the first to n-th resistor circuits to the external terminal, n being an integer of 2 or greater; first to n-th three-state drivers respectively supplying first to n-th amplified signals, which are obtained by amplifying the input signal, to the first to n-th resistor circuits, each at the other end thereof; and an output impedance adjusting circuit configured to supply first to n-th enable-disable signals to the first to n-th three-state drivers, respectively, to thereby enable or disable the first to n-th three-state drivers.