# US 2017/0288609 A1 · Multi-mode stacked amplifier > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0288609 A1 - Document ID: US20170288609A1 - Status: Published application - Kind: A1 - Application number: 15/474,905 - Filed: 2017-03-30 - Published: 2017-10-05 - Earliest claimed: 2016-04-01 - Assignees: Skyworks Solutions, Inc. - Applicants: Skyworks Solutions, Inc. - Inventors: Yasser Khairat Soliman - Web page: https://patentgrep.com/patent/US20170288609A1 ## CPC - H03F 1/0216: {Continuous control} - H03F 1/0227: {using supply converters} - H03F 1/0266: {by using a signal derived from the input signal} - H03F 1/56: Modifications of input or output impedances, not otherwise provided for - H03F 3/195: in integrated circuits - H03F 3/213: in integrated circuits - H03F 3/245: {with semiconductor devices only} - H03F 2200/222: A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier - H03F 2200/294: the amplifier being a low noise amplifier [LNA] - H03F 2200/312: the loading circuit of an amplifying stage comprising one or more switches - H03F 2200/336: A I/Q, i.e. phase quadrature, modulator or demodulator being used in an amplifying circuit - H03F 2200/387: A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier - H03F 2200/411: the output amplifying stage of an amplifier comprising two power stages - H03F 2200/451: the amplifier being a radio frequency amplifier - H03F: AMPLIFIERS ## Abstract Aspects of this disclosure relate to an amplification circuit that includes a stacked amplifier and a bias circuit. The stacked amplifier includes at least a first transistor and a second transistor in series with each other. The stacked amplifier is operable in at least a first mode and a second mode. The bias circuit is configured to bias the second transistor to a linear region of operation in the first mode and to bias the second transistor as a switch in the second mode. In certain embodiments, the amplification circuit can be a power amplifier stage configured to receive a supply voltage that has a different voltage level in the first mode than in the second mode. ## Claims ### Claim 1 An amplification circuit comprising: a stacked amplifier including at least a first transistor and a second transistor in series with each other, the stacked amplifier operable in at least a first mode and a second mode; and a bias circuit configured to bias the second transistor to a linear region of operation in the first mode and to bias the second transistor as a switch in the second mode. ### Claim 2 (depends on 1) The amplification circuit of claim 1 wherein the stacked amplifier includes a third transistor in series with the first transistor and the second transistor. ### Claim 3 (depends on 1) The amplification circuit of claim 1 wherein the stacked amplifier is configured to amplify a radio frequency signal. ### Claim 4 (depends on 1) The amplification circuit of claim 1 wherein the bias circuit is configured to bias the second transistor in a saturation region of operation in the second mode. ### Claim 5 (depends on 1) The amplification circuit of claim 1 further comprising a first stage amplifier having an output electrically connected to an input of the stacked amplifier by way of a matching network. ### Claim 6 (depends on 1) The amplification circuit of claim 1 wherein the first transistor and the second transistor are semiconductor-on-insulator transistors. ### Claim 7 (depends on 1) The amplification circuit of claim 1 wherein the stacked amplifier is operable in a third mode, the bias circuit is configured to bias the second transistor to the linear region of operation in the third mode, and the stacked amplifier is configured to receive a supply voltage that has a different voltage level in the first mode than in the third mode. ### Claim 8 (depends on 1) The amplification circuit of claim 1 wherein the second mode is associated with a lower power than the first mode. ### Claim 9 (depends on 1) The amplification circuit of claim 1 wherein the stacked amplifier is configured to receive a supply voltage, the supply voltage having a lower voltage level in the second mode than in the first mode. ### Claim 10 (depends on 1) The amplification circuit of claim 1 further comprising an output matching network electrically connected to an output of the stacked amplifier, and the output matching network being either a class F output matching network or a class AB output matching network. ### Claim 11 A power amplifier system comprising: a power amplifier stage including at least a first transistor and a second transistor in series with each other, the power amplifier stage operable in at least a first mode and a second mode; a bias circuit configured to bias the second transistor to a linear region of operation in the first mode and to bias the second transistor as a switch in the second mode; and a supply control circuit configured to provide a supply voltage to the power amplifier stage such that the supply voltage has a higher voltage level in the first mode than in the second mode. ### Claim 12 (depends on 11) The power amplifier system of claim 11 wherein the supply control circuit is configured to receive a mode control signal and to adjust the voltage level of the supply voltage based on the mode control signal. ### Claim 13 (depends on 11) The power amplifier system of claim 11 wherein the supply control circuit is configured to provide the supply voltage such that the supply voltage has a different voltage level in a third mode than in both the first mode and the second mode. ### Claim 14 (depends on 11) The power amplifier system of claim 11 wherein the power amplifier stage includes a third transistor in series with the first transistor and the second transistor. ### Claim 15 (depends on 11) The power amplifier system of claim 11 wherein the bias circuit is configured to receive a mode control signal and to bias the second transistor based on the mode control signal. ### Claim 16 A front end system comprising: a low noise amplifier; a power amplifier circuit including a stacked amplifier including at least a first transistor and a second transistor in series with each other, the stacked amplifier operable in at least a first mode and a second mode, the power amplifier circuit further including a bias circuit configured to bias the second transistor to a linear region of operation in the first mode and to bias the second transistor as a switch in the second mode; and a switch electrically connected to the low noise amplifier and the power amplifier circuit. ### Claim 17 (depends on 16) The front end system of claim 16 wherein the switch is multi-throw switch having at least a first throw electrically coupled to the power amplifier circuit and a second throw electrically coupled to the low noise amplifier. ### Claim 18 (depends on 17) The front end system of claim 17 further comprising a bypass path electrically coupled to a third throw of the multi-throw switch. ### Claim 19 (depends on 16) The front end system of claim 16 wherein the low noise amplifier and the power amplifier circuit are embodied on a single die. ### Claim 20 (depends on 16) The front end system of claim 16 further comprising a package enclosing the power amplifier circuit, the low noise amplifier, and the switch.