# US 2017/0288559 A1 · Transformer

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- Number: US 2017/0288559 A1
- Document ID: US20170288559A1
- Status: Published application
- Kind: A1
- Application number: 15/509,296
- Filed: 2015-10-09
- Published: 2017-10-05
- Earliest claimed: 2014-11-05
- Assignees: Sumitomo Electric Industries, Ltd.; National University Corporation Toyohashi University of Technology
- Applicants: Sumitomo Electric Industries, Ltd.; National University Corporation Toyohashi University of Technology
- Inventors: Hideaki Nakahata; Kenichi Hirotsu; Takashi Ohira; Kyohei Yamada; Daiya Egashira
- Web page: https://patentgrep.com/patent/US20170288559A1

## CPC

- H02M 5/12: for conversion of voltage or current amplitude only
- H02M 3/158: including plural semiconductor devices as final control devices for a single load
- H02M 5/22: using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M 5/293: using semiconductor devices only
- H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P)

## Abstract

A transformer includes a front stage circuit and a rear stage circuit. As a front stage circuit, a switch series unit, which is connected in parallel to a power supply, includes odd-numbered switches and even-numbered switches alternately turned ON. Mutual connection points of the respective switches and points at both ends of the switch series unit are regarded as m nodes in total. Capacitors are provided on at least one of a first electrical path combining odd nodes to lead them to a first output port, and a second electrical path combining even nodes to lead them to a second output port. The capacitors are present so as to correspond to at least (m−1) nodes. The rear stage circuit includes an element series unit, which is composed of a pair of semiconductor elements connected in series to each other for conducting operations of mutually opposite polarities, and necessary inductors.

## Claims

### Claim 1

A transformer provided between a power supply and a load, and composed of a front stage circuit and a rear stage circuit, the transformer comprising:
as the front stage circuit,
a switch series unit composed of a plurality of switches, as many as a multiple of 2, connected in series with each other, the plurality of switches including odd-numbered switches and even-numbered switches as seen from one of both ends of the switch series unit, the odd-numbered switches and the even-numbered switches being configured to be alternately turned ON, the switch series unit as a whole being connected in parallel to the power supply, and
assuming that mutual connection points of the respective switches and points at the both ends of the switch series unit are regarded as m nodes in total and the nodes are seen in order of 1 to m from one of the both ends of the switch series unit, capacitors provided on at least one electrical path of a first electrical path and a second electrical path, the first electrical path being configured to combine odd nodes and lead the odd nodes to a first output port, the second electrical path being configured to combine even nodes and lead the even nodes to a second output port, the capacitors being present so as to correspond to at least (m−1) nodes;
as the rear stage circuit,
an element series unit composed of a pair of semiconductor elements that are connected in series to each other and perform conducting operations of mutually opposite polarities, one of both ends of the element series unit being connected to the first output port while the other end thereof being connected to the second output port, and
inductors provided on at least one electrical path of a third electrical path and a fourth electrical path, the third electrical path being configured to combine two nodes that are points at the both ends of the element series unit and to lead the two nodes to one of both ends of the load, the fourth electrical path being configured to lead one node that is a mutual connection point of the pair of semiconductor elements to the other end of the load, the inductors being present so as to correspond to at least two nodes of the three nodes in total; and
a control section configured to control ON/OFF operations of the switches.

### Claim 2 (depends on 1)

The transformer according to claim 1, wherein
assuming that a time period from a dead-time start time to a dead-time end time is a dead time τ, the dead-time start time being a time at which control for the odd-numbered switches and control for the even-numbered switches are both turned OFF, the dead-time end time being a time at which control for either the odd-numbered switches or the even-numbered switches is turned ON,
the control section, after the dead-time start time, calculates a first half time τ1 and a second half time τ2, the first half time τ1 being calculated on the basis of electric charges that move from the inductors to floating capacitances of the switches while one of the semiconductor elements is in a conductive state, the second half time τ2 being calculated on the basis of electric charges that move from the inductors to the floating capacitances of the switches while the other semiconductor element is in a conductive state, and the control section determines the dead time τ on the basis of the first half time τ1 and the second half time τ2.

### Claim 3 (depends on 2)

The transformer according to claim 2, wherein the control section terminates the dead time τ before the electric charges that have moved to the floating capacitances return to the inductors.

### Claim 4 (depends on 3)

The transformer according to claim 3, wherein
assuming that a switching cycle of the switches is T, an inductance of the inductors is L, and a resistance value of the load is R3, the dead time τ satisfies the following relationship:
τ1+τ2≦τ≦τ0+(τ2/2)+τ1
where
τ
0
=
T
4
-
L
2


R
3
τ
1
=
T
2
+
L

R
3
-
1
2

(
T
+
2

L
R
3
)
2
-
32


L

∑
n
=
1
n


C
nDS
τ
2
=
T
2
-
L

R
3
-
1
2

(
T
-
2

L
R
3
)
2
-
32


L

∑
n
=
1
n


C
nDS
where n denotes the number of floating capacitances CDS, CnDS denotes an n-th floating capacitance, a sign of a value in each radical sign is plus, and τ1<τ2 is satisfied.

### Claim 5 (depends on 3)

The transformer according to claim 3, wherein assuming that a switching cycle of the switches is T, an inductance, of inductances of the inductors, that is dominant for the dead time is L1, and a resistance value of the load is R3, the dead time τ satisfies the following relationship:
τ1+τ2≦τ≦τ0+τ1
where
τ
0
=
T
4
-
L
1
4

R
3
τ
1
=
T
4
+
L
1

4

R
3
-
1
4

(
T
+
L
1
R
3
)
2
-
32


L
1

∑
n
=
1
n


C
nDS
τ
2
=
T
4
-
L
1

4

R
3
-
1
4

(
T
-
L
1
R
3
)
2
-
32


L
1

∑
n
=
1
n


C
nDS
where n denotes the number of floating capacitances CDS, CnDS denotes an n-th floating capacitance, a sign of a value in each radical sign is plus, and τ1<τ2 is satisfied.