# US 2017/0288531 A1 · Charge pump circuit and method for operating a charge pump circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0288531 A1 - Document ID: US20170288531A1 - Status: Published application - Kind: A1 - Application number: 15/086,922 - Filed: 2016-03-31 - Published: 2017-10-05 - Earliest claimed: 2016-03-31 - Assignees: NXP B.V. - Applicants: NXP B.V. - Inventors: Ivan Carlos Ribeiro do Nascimento - Web page: https://patentgrep.com/patent/US20170288531A1 ## CPC - H02M 3/07: using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) ## Abstract Embodiments of a charge pump circuit and a method for operating a charge pump circuit are disclosed. In an embodiment, a charge pump circuit includes a charge pump configured to generate a charge pump output voltage, a transistor array including multiple transistor devices that includes at least one transistor device having a back gate terminal coupled to the charge pump output voltage, and a control circuit configured to control the charge pump output voltage so as to regulate the back bias voltage of the transistor devices within the transistor array. Other embodiments are also described. ## Claims ### Claim 1 A charge pump circuit, the charge pump circuit comprising: a charge pump configured to generate a charge pump output voltage; a transistor array comprising a plurality of transistor devices, wherein the transistor devices includes at least one transistor device having a back gate terminal coupled to the charge pump output voltage, wherein the transistor array comprises: a first transistor device, wherein a gate terminal and a drain terminal of the first transistor device are connected to each other and to a first input terminal of the charge pump, and wherein a back gate terminal of the first transistor device is coupled to the charge pump output voltage; and a second transistor device, wherein a gate terminal and a drain terminal of the second transistor device are connected to each other and to a second input terminal of the charge pump, and wherein a back gate terminal and a source terminal of the second transistor device coupled to a fixed voltage that is different from the charge pump output voltage; and a control circuit configured to control the charge pump output voltage so as to regulate the back bias voltage of the first transistor device within the transistor array. ### Claim 2 (canceled) ### Claim 3 (canceled) ### Claim 4 (depends on 1) The charge pump circuit of claim 1, wherein the control circuit comprises: a first current source connected to the gate terminal and the drain terminal of the first transistor device, to the first input terminal of the charge pump, and to a second fixed voltage; and a second current source connected to the gate terminal and the drain terminal of the second transistor device, to the second input terminal of the charge pump, and to the second fixed voltage. ### Claim 5 (depends on 4) The charge pump circuit of claim 4, wherein the first and second transistor devices are of the same type, and wherein a ratio between a gate width of the first transistor device and a gate length of the first transistor device is different from a ratio between a gate width of the second transistor device and a gate length of the second transistor device. ### Claim 6 (depends on 4) The charge pump circuit of claim 4, wherein the first and second transistor devices are of the same type, and wherein a current level of the first current source is different from a current level of the second current source. ### Claim 7 (depends on 4) The charge pump circuit of claim 4, wherein the fixed voltage is a positive fixed voltage, wherein the first and second transistor devices are PMOS transistors with source terminals connected to the positive fixed voltage, and wherein the first and second current sources are connected to ground. ### Claim 8 (depends on 4) The charge pump circuit of claim 4, wherein the first and second transistor devices are NMOS transistors with source terminals connected to ground, and wherein the first and second current sources are connected to a positive voltage. ### Claim 9 (depends on 1) The charge pump circuit of claim 1, wherein the control circuit comprises: a first current source connected to the gate terminal and the drain terminal of the first transistor device, to a first input terminal of the charge pump, and to a second fixed voltage; a resistor connected to the gate terminal and to the drain terminal of the second transistor device; and a second current source connected to the resistor, to a second input terminal of the charge pump, and to the second fixed voltage. ### Claim 10 (depends on 9) The charge pump circuit of claim 9, wherein the first and second transistor devices are of the same type, and wherein a ratio between a gate width of the first transistor device and a gate length of the first transistor device is equal to a ratio between a gate width of the second transistor device and a gate length of the second transistor device. ### Claim 11 (depends on 1) The charge pump circuit of claim 1, wherein a gate terminal and a source terminal of each of the transistor devices of the transistor array are connected to each other, and wherein a back gate terminal of each of the transistor devices is coupled to the charge pump output voltage. ### Claim 12 (depends on 11) The charge pump circuit of claim 11, wherein the gate terminal and the source terminal of each of the transistor devices are coupled to a fixed voltage. ### Claim 13 (depends on 12) The charge pump circuit of claim 12, wherein the control circuit comprises: a current source connected to the drain terminal of each of the transistor devices and to a second fixed voltage; a capacitor connected to the drain terminal of each of the transistor devices and to the second fixed voltage; a Schmitt trigger with an inverted output connected to the drain terminal of each of the transistor devices; and an inverter connected to an output terminal of the Schmitt trigger and to an input terminal of the charge pump. ### Claim 14 (depends on 12) The charge pump circuit of claim 12, wherein the control circuit comprises: a first current mirror connected to the gate terminal and to the source terminal of each of the transistor devices and to a second fixed voltage; a second current mirror connected to the gate terminal and to the source terminal of each of the transistor devices and to the first current mirror; a capacitor connected to the drain terminal of each of the transistor devices and to the second fixed voltage; a current source connected to the second current mirror and to the second fixed voltage; and a Schmitt trigger with an inverted output connected to the first and second current mirrors and to an input terminal of the charge pump. ### Claim 15 (depends on 12) The charge pump circuit of claim 12, wherein the transistor devices are of the same type, and wherein a ratio between a gate width of a first transistor device of the transistor devices and a gate length of the first transistor device is the same as a ratio between a gate width of a second transistor device of the transistor devices and a gate length of the second transistor device. ### Claim 16 A charge pump circuit, the charge pump circuit comprising: a charge pump configured to generate a charge pump output voltage; a transistor array comprising a plurality of PMOS transistors, wherein a gate terminal and a source terminal of each of the PMOS transistors are connected to each other, wherein a back gate terminal of each of the PMOS transistors is coupled to the charge pump output voltage, and wherein the gate terminal and the source terminal of each of the transistors are coupled to a fixed voltage; and a control circuit configured to control the charge pump output voltage so as to regulate the back bias voltage of the PMOS transistors within the transistor array. ### Claim 17 (depends on 16) The charge pump circuit of claim 16, wherein the control circuit comprises: a current source connected to the drain terminal of each of the PMOS transistors and to ground; a capacitor connected to the drain terminal of each of the PMOS transistors and to ground; a Schmitt trigger connected to the drain terminal of each of the PMOS transistors; and an inverter connected to an output terminal of the Schmitt trigger and to an input terminal of the charge pump. ### Claim 18 (depends on 16) The charge pump circuit of claim 16, wherein the control circuit comprises: a first current mirror connected to the gate terminal and the source terminal of each of the PMOS transistors and to ground; a second current mirror connected to the gate terminal and the source terminal of each of the PMOS transistors and to the first current mirror; a capacitor connected to the drain terminal of each of the PMOS transistors and to ground; a current source connected to the second current mirror and to ground; and a Schmitt trigger connected to the first and second current mirrors and to an input terminal of the charge pump. ### Claim 19 (depends on 16) The charge pump circuit of claim 16, wherein a ratio between a gate width of a first PMOS transistor of the PMOS transistors and a gate length of the first PMOS transistor is the same as a ratio between a gate width of a second PMOS transistor of the PMOS transistors and a gate length of the second PMOS transistor. ### Claim 20 A method for operating a charge pump circuit, the method comprising: generating a charge pump output voltage; operating a transistor array of the charge pump circuit in response to the charge pump output voltage, wherein the transistor array comprises: a first transistor device, wherein a gate terminal and a drain terminal of the first transistor device are connected to each other and to a first input terminal of the charge pump, and wherein a back gate terminal of the first transistor device is coupled to the charge pump output voltage; and a second transistor device, wherein a gate terminal and a drain terminal of the second transistor device are connected to each other and to a second input terminal of the charge pump, and wherein a back gate terminal and a source terminal of the second transistor device are coupled to a fixed voltage that is different from the charge pump output voltage; and controlling the charge pump output voltage so as to regulate the back bias voltage of the first transistor device within the transistor array.