# US 2017/0288391 A1 · Fail-Safe For Shared Pin

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- Number: US 2017/0288391 A1
- Document ID: US20170288391A1
- Status: Published application
- Kind: A1
- Application number: 15/087,089
- Filed: 2016-03-31
- Published: 2017-10-05
- Earliest claimed: 2016-03-31
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Sumit Dubey; Nitin Agarwal
- Web page: https://patentgrep.com/patent/US20170288391A1

## CPC

- H02H 3/20: responsive to excess voltage
- H02H: EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS (indicating or signalling undesired working conditions G01R, e.g. G01R31/00, G08B; locating faults along lines G01R31/08; emergency protective devices H01H)

## Abstract

An integrated circuit (IC) provides an improved fail-safe signal to a circuit sharing a fail-safe pin at which the voltage can be greater than the voltage of an upper rail. The IC includes a first circuit segment that receives a first fail-safe signal and a first power-down signal and provides an intermediate signal, wherein the first fail-safe signal indicates when the voltage at the fail-safe pin is greater than the upper rail and the first power-down signal indicates when the module is powered down, and a second circuit segment connected to receive the intermediate signal and to provide the improved fail-safe signal to the module.

## Claims

### Claim 1

An integrated circuit (IC) for providing an improved fail-safe signal to a circuit sharing a fail-safe pin at which a voltage can be greater than a voltage of an upper rail, the IC comprising:
a first circuit segment that receives a first fail-safe signal and a first power-down signal and provides an intermediate signal, wherein the first fail-safe signal indicates when the voltage at the fail-safe pin is greater than the upper rail and the first power-down signal indicates when the module is powered down; and
a second circuit segment connected to receive the intermediate signal and to provide the improved fail-safe signal to the module.

### Claim 2 (depends on 1)

The IC as recited in claim 1 wherein the first circuit segment is coupled between a second power-down signal that is the inverse of the first power-down signal and a lower rail.

### Claim 3 (depends on 2)

The IC as recited in claim 2 wherein the second circuit segment is coupled between a high signal that is the higher of the upper rail and the voltage at the fail-safe pin.

### Claim 4 (depends on 3)

The IC as recited in claim 3 wherein the first circuit segment comprises:
a first PMOS transistor coupled in series with a first NMOS transistor;
a second NMOS transistor coupled in parallel with the first NMOS transistor; and
further wherein the first fail-safe signal is coupled to drive a gate of the first PMOS transistor and a gate of the second NMOS transistor and the second power-down signal is coupled to drive a gate of the first NMOS transistor.

### Claim 5 (depends on 4)

The IC as recited in claim 4, wherein the second circuit comprises a second PMOS transistor coupled in series with a third NMOS transistor, the intermediate signal being coupled to drive a gate of the second PMOS transistor and a gate of the third NMOS transistor and the improved fail-safe signal being taken from a point between the second PMOS transistor and the third NMOS transistor.

### Claim 6 (depends on 5)

The IC as recited in claim 5 wherein the body of the first PMOS transistor and the body of the second PMOS transistor are coupled to the high signal.

### Claim 7 (depends on 6)

The IC as recited in claim 6 wherein the first fail-safe signal is provided by a third circuit segment coupled between the fail-safe pin and the lower rail.

### Claim 8 (depends on 7)

The IC as recited in claim 7 wherein the third circuit segment comprises a third and a fourth PMOS transistor coupled in series with a fourth NMOS transistor, a gate of the third PMOS transistor and a gate of the fourth NMOS transistor being controlled by the upper rail and a gate of the fourth PMOS transistor being controlled by the lower rail and further wherein the body of the third PMOS transistor and the body of the fourth PMOS transistor are coupled to the high signal.

### Claim 9 (depends on 8)

The IC chip as recited in claim 8 wherein the high signal is provided by a fourth circuit segment coupled between the fail-safe pin and the upper rail.

### Claim 10 (depends on 9)

The IC chip as recited in claim 9 wherein the fourth circuit segment comprises a fifth PMOS transistor coupled in series with a fifth NMOS transistor, the gate of the fifth PMOS transistor being controlled by the upper rail and the gate of the fifth NMOS transistor being controlled by the first fail-safe signal, the high signal being taken at a point between the fifth PMOS transistor and the fifth NMOS transistor and further wherein the substrate of the fifth NMOS transistor and the fifth PMOS transistor are coupled to the high signal.

### Claim 12

An integrated circuit (IC) chip comprising:
a plurality of circuit blocks that share a common pin, wherein a voltage at the common pin can be greater than a voltage of an upper rail;
a first circuit block of the plurality of circuit blocks, the first circuit block comprising a PMOS transistor coupled in series between the common pin and the upper rail; and
a fail-safe circuit that receives the voltage at the common pin and a power-down signal for the first circuit block and provides a first fail-safe signal that turns off the PMOS transistor whenever the voltage at the common pin is greater than the upper rail and also when the first circuit block is in power-down mode.