# US 2017/0288141 A1 · Socket structure for three-dimensional memory

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- Number: US 2017/0288141 A1
- Document ID: US20170288141A1
- Status: Published application
- Kind: A1
- Application number: 15/623,030
- Filed: 2017-06-14
- Published: 2017-10-05
- Earliest claimed: 2015-04-24
- Assignees: Sony Corporation
- Applicants: Sony Corporation
- Inventors: Jun Sumino
- Web page: https://patentgrep.com/patent/US20170288141A1

## CPC

- H10N 70/011: {Manufacture or treatment of multistable switching devices}
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/35: with a cell select transistor, e.g. NAND
- H10B 41/50: characterised by the boundary region between the core region and the peripheral circuit region
- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 43/35: with cell select transistors, e.g. NAND
- H10B 43/50: characterised by the boundary region between the core and peripheral circuit regions
- H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays}
- H10W 20/01: {Manufacture or treatment}
- H10W 20/42: Vias, e.g. via plugs
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B: ELECTRONIC MEMORY DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Socket structures that are configured to use area efficiently, and methods for providing socket regions that use area efficiently, are provided. The staircase type contact area or socket region includes dielectric layers between adjacent planar electrodes that partially cover a portion of a planar electrode that does directly underlie an adjacent planar electrode. The portion of a dielectric layer between adjacent planar electrodes can be sloped, such that it extends from an edge of an overlying planar electrode to a point between the edge of an underlying planar electrode and a point corresponding to an edge of the overlying planar electrode.

## Claims

### Claim 1

A memory structure, comprising:
a plurality of memory arrays configured to be stacked, wherein each of the memory arrays includes a plurality of memory cells;
a plurality of word lines configured to be coupled to the plurality of the memory cells via a plurality of electrodes;
a plurality of dielectric layers configured to be located between the electrodes;
a socket region configured to be located along one side of the memory arrays;
a plurality of conductors configured to be located between each of the word lines and each of the electrodes.

### Claim 2 (depends on 1)

The memory structure of the claim 1, wherein a part of the plurality of the conductors is located in the socket region.

### Claim 3 (depends on 1)

The memory structure of the claim 1, wherein the plurality of the electrodes extend to the memory arrays.

### Claim 4 (depends on 1)

The memory structure of the claim 1, further comprising:
a plurality of bit lines configured to be coupled to the plurality of the memory cells.

### Claim 5 (depends on 1)

The memory structure of the claim 1, wherein the plurality of the electrodes are stacked in a vertical dimension.

### Claim 6 (depends on 5)

The memory structure of the claim 5, wherein adjacent electrodes are separated from one another in the vertical dimension by at least one of the dielectric layers.

### Claim 7 (depends on 1)

The memory structure of the claim 1, wherein the plurality of the electrodes extend from an area of the stacked memory arrays to the socket region.

### Claim 8 (depends on 1)

The memory structure of the claim 1, wherein an edge of each of the dielectric layers disposed between the electrodes is located between an edge of first electrode and an edge of second electrode.

### Claim 9 (depends on 1)

The memory structure of the claim 1, wherein each of the plurality of the electrodes includes a portion that is not covered by each of the plurality of the dielectric layers within the socket region such that each of the horizontal electrodes is accessible along one or more lines that are parallel to the vertical dimension.

### Claim 10 (depends on 8)

The memory structure of claim 8, wherein the edge of each of the dielectric layers is sloped.

### Claim 11 (depends on 10)

The memory structure of claim 10, wherein the edges of the first and second electrodes are vertical.