# US 2017/0288064 A1 · Semiconductor device, manufacturing method thereof, and electronic device

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- Number: US 2017/0288064 A1
- Document ID: US20170288064A1
- Status: Published application
- Kind: A1
- Application number: 15/628,699
- Filed: 2017-06-21
- Published: 2017-10-05
- Earliest claimed: 2015-06-19
- Assignees: Semiconductor Energy Laboratory Co., Ltd.
- Applicants: Semiconductor Energy Laboratory Co., Ltd.
- Inventors: Daigo ITO; Daisuke MATSUBAYASHI; Masaharu NAGAI; Yoshiaki YAMAMOTO; Takashi HAMADA; Yutaka OKAZAKI; Shinya SASAGAWA; Motomu KURATA; Naoto YAMADE
- Web page: https://patentgrep.com/patent/US20170288064A1

## CPC

- H10D 30/6756: {Amorphous oxide semiconductors}
- H10D 30/6213: {having rounded corners}
- H10D 30/6215: {having multiple independently-addressable gate electrodes}
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 86/0212: {comprising manufacture, treatment or coating of substrates}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10D 86/60: wherein the TFTs are in active matrices
- H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
- H10D 99/00: Subject matter not provided for in other groups of this subclass
- H10P 30/202: {characterised by the semiconductor materials}
- H10P 30/208: {of electrically inactive species}
- H10P 30/21: {of electrically active species}
- H10P 30/22: using masks
- H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10D 30/473: {having confinement of carriers by multiple heterojunctions, e.g. quantum well HEMT}
- H10D 30/6719: {having significant overlap between the lightly-doped drains and the gate electrodes, e.g. gate-overlapped LDD [GOLDD] TFTs}
- H10D 62/80: characterised by the materials
- H10D 62/875: {being semiconductor metal oxide, e.g. InGaZnO (Group II-VI materials H10D62/86; Group I-VI materials H10D62/871; Pb compounds or alloys H10D62/874)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer. The second and third regions each include a region containing an element N (N is phosphorus, argon, or xenon).

## Claims

### Claim 1

A semiconductor device comprising:
a first insulating layer over a substrate;
a first metal oxide layer over the first insulating layer;
an oxide semiconductor layer over the first metal oxide layer;
a second metal oxide layer over the oxide semiconductor layer;
a gate insulating layer over the second metal oxide layer; and
a gate electrode layer over the gate insulating layer,
wherein the oxide semiconductor layer comprises a first region, a second region, and a third region,
wherein the first region and the second region each comprise a region overlapping with the gate electrode layer,
wherein the second region is between the first region and the third region,
wherein the second region comprises a region with lower resistance than the first region,
wherein the third region comprises a region with lower resistance than the second region,
wherein the second region and the third region each comprise a region containing an element N, and
wherein N is phosphorus, argon, or xenon.

### Claim 2

A semiconductor device comprising:
a first insulating layer over a substrate;
a first metal oxide layer over the first insulating layer;
an oxide semiconductor layer over the first metal oxide layer;
a second metal oxide layer over the first insulating layer and the oxide semiconductor layer;
a first gate insulating layer over the second metal oxide layer; and
a gate electrode layer over the first gate insulating layer,
wherein the second metal oxide layer and the first gate insulating layer each comprise a region facing side surfaces of the first metal oxide layer and the oxide semiconductor layer,
wherein the oxide semiconductor layer comprises a first region, a second region, and a third region,
wherein the first region and the second region each comprise a region overlapping with the gate electrode layer,
wherein the second region is between the first region and the third region,
wherein the second region comprises a region with lower resistance than the first region,
wherein the third region comprises a region with lower resistance than the second region,
wherein the second region and the third region each comprise a region containing an element N, and
wherein N is phosphorus, argon, or xenon.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2, wherein a second gate insulating layer is between the first gate insulating layer and the gate electrode layer.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the second region comprises a region containing the element N at a higher concentration than that in the first region, and the third region comprises a region containing the element N at a higher concentration than that in the second region.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein the third region comprises a region containing the element N at a concentration higher than or equal to 1×1018 atoms/cm3 and lower than or equal to 1×1022 atoms/cm3.

### Claim 6

A semiconductor device comprising:
a first insulating layer over a substrate;
a first metal oxide layer over the first insulating layer;
an oxide semiconductor layer over the first metal oxide layer;
a second metal oxide layer over the oxide semiconductor layer;
a gate insulating layer over the second metal oxide layer;
a second insulating layer over the second metal oxide layer; and
a gate electrode layer over the gate insulating layer,
wherein the gate insulating layer comprises a region in contact with a side surface of the gate electrode layer,
wherein the second insulating layer comprises a region in contact with the gate insulating layer,
wherein the oxide semiconductor layer comprises a first region, a second region, and a third region,
wherein the first region comprises a region overlapping with the gate electrode layer,
wherein the second region comprises a region overlapping with the gate insulating layer or the second insulating layer,
wherein the second region is between the first region and the third region,
wherein the second region and the third region each comprise a region containing an element N, and
wherein N is phosphorus, argon, or xenon.

### Claim 7 (depends on 6)

The semiconductor device according to claim 6, wherein the second region comprises a region with lower resistance than the first region, and the third region comprises a region with lower resistance than the second region.

### Claim 8 (depends on 6)

The semiconductor device according to claim 6 further comprising a region where an angle between a bottom surface of the substrate and a tangent of a side surface of the gate electrode layer is greater than or equal to 60° and less than or equal to 85°.

### Claim 9 (depends on 1)

An electronic device comprising:
the semiconductor device according to claim 1;
a housing; and
a speaker.