# US 2017/0288058 A1 · Electrostatic discharge device

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- Number: US 2017/0288058 A1
- Document ID: US20170288058A1
- Status: Published application
- Kind: A1
- Application number: 15/624,741
- Filed: 2017-06-16
- Published: 2017-10-05
- Earliest claimed: 2013-11-25
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Aravind C. Appaswamy; Akram A. Salman; Farzan Farbiz; Gianluca Boselli
- Web page: https://patentgrep.com/patent/US20170288058A1

## CPC

- H10D 30/603: {having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended drain IGFETs [EDMOS]}
- H10D 62/378: {Contact regions to the substrate regions}
- H10D 89/813: {specially adapted to provide an electrical current path other than the field-effect induced current path}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a body and a transistor fabricated into the body. Isolation material at least partially encases the body. Biasing is coupled to the isolation material, wherein the biasing is for changing the electric potential of the isolation material in response to an electrostatic discharge event.

## Claims

### Claim 1

A device, comprising:
a substrate having a top surface;
an n-type region extending from the top surface;
a p-type region within the n-type region and extending from the top surface;
a first n+ region within the p-type region and separated from the n-type region by the p-type region;
a second n+ region within the p-type region and separated from the n-type region and the first n+ region by the p-type region; and
an impedance above the top surface, and coupled between the n-type region and the second n+ region.

### Claim 2 (depends on 1)

The device of claim 1, wherein each of the first n+ region and the second n+ region has a higher dopant concentration than the n-type region and the p-type region.

### Claim 3 (depends on 1)

The device of claim 1, wherein the impedance includes a resistor.

### Claim 4 (depends on 1)

The device of claim 1, wherein the impedance includes a transistor having:
a gate coupled to a voltage supply terminal;
a drain coupled to the second n+ region; and
a source coupled to the n-type region.

### Claim 5 (depends on 1)

The device of claim 1, wherein the impedance includes a transistor having:
a gate coupled to a voltage supply terminal;
a source coupled to the second n+ region; and
a drain coupled to the n-type region.

### Claim 6 (depends on 1)

The device of claim 1, further comprising:
a Zener diode having an anode coupled to the n-type region, and a cathode coupled to the first n+ region. The device of claim 1, further comprising:
a capacitor having a first terminal coupled to the n-type region, and a second terminal coupled to the first n+ region.

### Claim 8 (depends on 1)

The device of claim 1, further comprising:
a drain-extended MOS transistor having:
a drain contact in the first n+ region;
a source contact in the second n+ region;
a body contact in the p-type region; and
a gate above the top surface and between the drain contact and the source contact.

### Claim 9 (depends on 1)

The device of claim 1, further comprising:
an isolation structure in the n-type region, the isolation structure includes a layer under the p-type region, and a sidewall laterally surrounding the p-type region.

### Claim 10 (depends on 1)

The device of claim 1, further comprising:
an n-well interfacing between the first n+ region and the p-type region, the n-well having
a lower dopant concentration than the first n+ region;
a vertical NPN structure having:
a first collector region in the n-well;
a first base region in the p-type region; and
a first emitter region in the second n+ region; and
a horizontal NPN structure having:
a second collector region in the n-well;
a second base region in the p-type region; and
a second emitter region in the n-type region.

### Claim 11

A device, comprising:
a substrate having a top surface;
an n-type region extending from the top surface;
a p-type region within the n-type region and extending from the top surface;
a first n+ region within the p-type region and separated from the n-type region by the p-type region;
a second n+ region within the p-type region and separated from the n-type region and the first n+ region by the p-type region; and
a resistor above the top surface, and coupled between the n-type region and the second n+ region.

### Claim 12 (depends on 11)

The device of claim 11, wherein each of the first n+ region and the second n+ region has a higher dopant concentration than the n-type region and the p-type region.

### Claim 13 (depends on 11)

The device of claim 11, further comprising:
a Zener diode having an anode coupled to the n-type region, and a cathode coupled to the first n+ region.

### Claim 14 (depends on 11)

The device of claim 11, further comprising:
a capacitor having a first terminal coupled to the n-type region, and a second terminal coupled to the first n+ region.

### Claim 15 (depends on 11)

The device of claim 11, further comprising:
a drain-extended MOS transistor having:
a drain contact in the first n+ region;
a source contact in the second n+ region;
a body contact in the p-type region; and
a gate above the top surface and between the drain contact and the source contact.

### Claim 16 (depends on 11)

The device of claim 11, further comprising:
an isolation structure in the n-type region, the isolation structure includes a buried layer under the p-type region, and a sidewall laterally surrounding the p-type region;
an n-well interfacing between the first n+ region and the p-type region, the n-well having a lower dopant concentration than the first n+ region;
a vertical NPN structure having:
a first collector region in the n-well;
a first base region in the p-type region; and
a first emitter region in the second n+ region; and
a horizontal NPN structure having:
a second collector region in the n-well;
a second base region in the p-type region; and
a second emitter region in the buried layer of the isolation structure.

### Claim 17

A device, comprising:
a substrate having a top surface;
an n-type region extending from the top surface;
a p-type region within the n-type region and extending from the top surface;
a first n+ region within the p-type region and separated from the n-type region by the p-type region;
a second n+ region within the p-type region and separated from the n-type region and the first n+ region by the p-type region; and
a p-well within the n-type region and outside the p-type region, the p-well extending from the top surface.

### Claim 18 (depends on 17)

The device of claim 17, further comprising:
a conductor above the top surface, and coupled between the p-well and the first n+ region.

### Claim 19 (depends on 17)

The device of claim 17, further comprising:
a bias voltage terminal above the top surface, and coupled to the p-well.

### Claim 20 (depends on 17)

The device of claim 17, further comprising:
a drain-extended MOS transistor having:
a drain contact in the first n+ region;
a source contact in the second n+ region;
a body contact in the p-type region; and
a gate above the top surface and between the drain contact and the source contact.