# US 2017/0288050 A1 · Semiconductor device and production method therefor

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- Number: US 2017/0288050 A1
- Document ID: US20170288050A1
- Status: Published application
- Kind: A1
- Application number: 15/464,112
- Filed: 2017-03-20
- Published: 2017-10-05
- Earliest claimed: 2016-03-29
- Assignees: Toyoda Gosei Co., Ltd.
- Applicants: Toyoda Gosei Co., Ltd.
- Inventors: Yukihisa UENO; Nariaki TANAKA
- Web page: https://patentgrep.com/patent/US20170288050A1

## CPC

- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/665: {having edge termination structures}
- H10D 62/104: {having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats}
- H10D 62/105: {by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] (IGFETs having LDD or drain extension regions H10D30/601)}
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 62/154: {Dispositions}
- H10D 62/158: {Dispositions}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D 64/111: {Field plates}
- H10P 30/206: {into Group III-V semiconductors}
- H10P 30/208: {of electrically inactive species}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

To improve the breakdown voltage of a semiconductor device. In a terminal region of the semiconductor device, a mesa groove, a recess groove, an electric field relaxation region, and a gradient distributed low concentration p-type layer region are formed. A recess groove is fromed between a device region and the mesa groove so as to surround the device region. A region where a p-type layer is thinned by the recess groove is the electric field relaxation region. The gradient distributed low concentration p-type layer region is formed on the surface of the electric field relaxation region. The average carrier concentration of the entire gradient distributed low concentration p-type layer region is lower than the carrier concentration of the p-type layer. By forming the gradient distributed low concentration p-type layer region, the electric field relaxation region is quickly completely depleted when a reverse voltage is applied, thereby improving the breakdown voltage.

## Claims

### Claim 1

A semiconductor device comprising:
a device region positioned in a center of a device and serving as an operating region of the device; and
a terminal region formed in a periphery of the device region and surrounding the device region;
the device region comprising:
a first conductivity type first layer;
a second conductivity type second layer formed on the first layer; and
an interface between the first layer and the second layer being exposed on the end surfaces of the first layer and the second layer,
wherein the terminal region comprises:
a mesa groove surrounding the device region and having a depth reaching from the surface of the second layer to the first layer;
a recess groove being formed between the device region and the mesa groove so as to surround the device region and including an electric field relaxation region formed by thinning the second layer; and
a second conductivity type third layer being formed in the electric field relaxation region and having a carrier concentration lower than a carrier concentration of the second layer.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the mesa groove and the recess groove are continuously formed in a two-step shape, and the side surface on the device region side of the mesa groove is flush with the side surface on the mesa groove side of the third layer.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein the side surface on the recess groove side of the third layer is outside the side surface on the device region side of the recess groove.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein the third layer has a carrier concentration distribution in which the carrier concentration is gradually increased from the surface of the electric field relaxation region toward the first layer.

### Claim 5 (depends on 4)

The semiconductor device according to claim 4, further comprising a first conductivity type fourth layer formed in the device region of the second layer, and a second conductivity type fifth layer being formed in the second layer on the first layer side of the fourth layer and having a carrier concentration distribution in which the carrier concentration is gradually increased from the fourth layer toward the first layer.

### Claim 6 (depends on 5)

The semiconductor device according to claim 5, wherein the bottom surface of the third layer is closer to the first layer than the bottom surface of the fifth layer is to the first layer.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, further comprising a first conductivity type fourth layer formed in the device region of the second layer, wherein only the second layer exists between the fourth layer and the first layer.

### Claim 8 (depends on 7)

The semiconductor device according to claim 7, wherein the bottom surface of the third layer reaches an interface between the first layer and the second layer.

### Claim 9 (depends on 5)

The semiconductor device according to claim 5, wherein the bottom surface of the third layer is flush with the bottom surface of the fifth layer, and the second layer exists between the bottom surfaces of the third layer and the fifth layer and the interface between the first layer and the second layer.

### Claim 10 (depends on 5)

The semiconductor device according to claim 5, wherein the semiconductor device is a field effect transistor in which the first layer is a drift region, the second layer is a body region, and the fourth layer is a source region.

### Claim 11 (depends on 1)

The semiconductor device according to claim 1, wherein the width of the third layer is 5 μm or more.

### Claim 12 (depends on 1)

The semiconductor device according to claim 1, wherein semiconductor device comprises Group III nitride semiconductor.

### Claim 13

A method for producing a semiconductor device comprising:
forming a device region including a first conductivity type first layer, a second conductivity type second layer formed on the first layer, and an interface between the first layer and the second layer exposed on the end surfaces of the first layer and the second layer; and
forming a terminal region surrounding the device region, wherein the method comprising:
forming first conductivity type fourth layer in the terminal region and the device region respectively of the second layer by ion implantation into the terminal region and the device region of the second layer respectively;
forming a third layer and a fifth layer in the second layer of the terminal region and the device region respectively by the ion implantation to form the fourth layer such that the third layer and the fifth layer have a carrier concentration distribution in which the carrier concentration is gradually increased toward the first layer;
forming a mesa groove surrounding the device region and having a depth reaching from the surface of the second layer to the first layer, thereby the fourth layer disposed above the third layer being removed; and
forming a recess groove surrounding the device region between the device region and the mesa groove and having an electric field relaxation region of the thinned second layer, thereby the fourth layer disposed above the third layer being removed.