# US 2017/0288043 A1 · Power semiconductor device

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- Number: US 2017/0288043 A1
- Document ID: US20170288043A1
- Status: Published application
- Kind: A1
- Application number: 15/623,952
- Filed: 2017-06-15
- Published: 2017-10-05
- Earliest claimed: 2015-03-30
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation
- Inventors: Dae Sub JUNG; Bo LIU
- Web page: https://patentgrep.com/patent/US20170288043A1

## CPC

- H10D 12/441: {Vertical IGBTs}
- H10D 12/032: {of vertical IGBTs}
- H10D 12/461: {having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions}
- H10D 62/109: {Reduced surface field [RESURF] PN junction structures}
- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H10D 62/137: {Collector regions of BJTs}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 62/60: Impurity distributions or concentrations
- H10D 62/82: Heterojunctions
- H10P 14/24: using chemical vapour deposition [CVD]
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3456: {Polycrystalline}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 30/28: characterised by an annealing step, e.g. for activation of dopants
- H10P 50/642: {Chemical etching}
- H10P 52/402: {of semiconductor materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for forming a power semiconductor device is provided. The method includes providing a substrate having a first surface and a second surface; and forming a plurality of trenches in the second surface of the substrate. The method also includes forming a semiconductor pillar in each of the plurality of trenches, wherein the semiconductor pillars and the substrate form a plurality of super junctions of the power semiconductor device for increasing the breakdown voltage of the power semiconductor device and reducing the on-stage voltage of the power semiconductor device; and forming a gate structure on the first surface of the substrate. Further, the method includes forming a plurality of well regions in the first surface of the substrate around the gate structure; and forming a source region in each of the plurality of well regions around the gate structure.

## Claims

### Claim at position 1

-15. (canceled)

### Claim 16

A power semiconductor device, comprising:
a substrate having a first surface and a facing second surface;
at least one gate structure formed on the first surface of the substrate;
a plurality of well regions formed in the first surface of the substrate around the gate structure;
a source region formed in each of the plurality of the well regions around the gate structure; and
a plurality of semiconductor pillars formed in the substrate, wherein the plurality of semiconductor pillars and the substrate form a plurality of super junctions of the power device for increasing the breakdown voltage of the power semiconductor device and reducing the on-stage voltage of the power semiconductor device.

### Claim 17 (depends on 16)

The power semiconductor device according to claim 16, further comprising
a buffer layer formed on the second surface of the substrate; and
a collector layer formed on the buffer layer.

### Claim 18 (depends on 16)

The power semiconductor device according to claim 16, wherein the semiconductor pillars are formed by:
forming a plurality of trenches in one surface of the substrate; and
filling a semiconductor material in each of the plurality of trenches.

### Claim 19 (depends on 16)

The power semiconductor device according to claim 16, wherein:
the substrate is doped with first type doping ions;
the semiconductor pillars are doped with second type doping ions opposite to the first type doping ions;
the source regions are doped with the first type doping ions; and
the well regions are doped with the second type doping ions.

### Claim 20 (depends on 16)

The power semiconductor device according to claim 16, wherein:
the semiconductor pillars are made of polysilicon.

### Claim 21 (depends on 16)

The power semiconductor device according to claim 16, further comprising
an interlayer dielectric layer formed on portions of the source regions close to the gate structure; and
a metal gate layer formed on top and side surfaces of the interlayer dielectric layer, wherein the metal gate layer covers portion of the source regions close to the well regions and portions of well regions close the source region.

### Claim 22 (depends on 16)

The power semiconductor device according to claim 16, wherein:
the substrate is a thinned substrate having a predetermined thickness.

### Claim 23 (depends on 16)

The power semiconductor device according to claim 16, wherein:
the semiconductor pillars are aligned with the well regions.

### Claim 24 (depends on 16)

The power semiconductor device according to claim 16, wherein:
the plurality of semiconductor pillars are evenly distributed in the substrate under the gate structure and the well regions.

### Claim 25 (depends on 16)

The power semiconductor device according to claim 16, wherein:
a product of a doping concentration of the semiconductor pillar and a width of the trench is equal to a product of a doping concentration of a portion of the substrate between adjacent semiconductor pillars and a width of the portion of the substrate between adjacent semiconductor pillars.