# US 2017/0288035 A1 · Pure boron for silicide contact

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- Number: US 2017/0288035 A1
- Document ID: US20170288035A1
- Status: Published application
- Kind: A1
- Application number: 15/629,910
- Filed: 2017-06-22
- Published: 2017-10-05
- Earliest claimed: 2015-07-29
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Chia-Yu Chen; Zuoguang Liu; Sanjay C. Mehta; Tenko Yamashita
- Web page: https://patentgrep.com/patent/US20170288035A1

## CPC

- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/0275: {forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/834: further characterised by the dopants
- H10D 64/01: Manufacture or treatment
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/251: {Source or drain electrodes for field-effect devices}
- H10D 64/254: {for lateral devices wherein the source or drain electrodes extend entirely through the semiconductor bodies, e.g. via-holes for back side contacts}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10D 64/259: {Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)}
- H10D 64/689: {having ferroelectric layers}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 32/14: within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
- H10P 32/1404: {using predeposition followed by drive-in of impurities into the semiconductor surface, e.g. predeposition from a gaseous phase}
- H10P 32/171: {being group IV material}
- H10P 50/242: {of Group IV materials}
- H10P 50/283: {by chemical means}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/0698: {Local interconnections}
- H10W 20/076: {in via holes or trenches}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10P 32/1408: {from or through or into an external applied layer, e.g. photoresist or nitride layers}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a gate disposed over a substrate; a source region and a drain region on opposing sides of the gate; and a pair of trench contacts over and abutting an interfacial layer portion of at least one of the source region and the drain region; wherein the interfacial layer includes boron in an amount in a range from about 5×1021 to about 5×1022 atoms/cm2.

## Claims

### Claim 1

A semiconductor device, comprising:
a gate disposed over a substrate;
a source region and a drain region on opposing sides of the gate; and
a pair of trench contact openings over and abutting an interfacial layer of at least one of the source region and the drain region, the interfacial layer comprising boron; and
a conformal layer comprising boron disposed within the pair of trench contact openings.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the conformal layer comprises amorphous boron.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the conformal layer comprises substantially pure boron.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the conformal layer comprises 100 atomic % boron.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the conformal layer comprises at least 98 atomic % boron.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the interfacial layer has a thickness in a range from about 0.5 to about 2 nanometers (nm).

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the pair of trench contacts have sidewalls that contact the interfacial layer.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the semiconductor device is a p-type field effect transistor (PFET).

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the trench contact comprises a high-k dielectric material.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the high-k dielectric material contacts the interfacial layer.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein the trench contact further comprises a conductive metal.

### Claim 12 (depends on 11)

The semiconductor device of claim 11, wherein the conductive metal is tungsten, aluminum, platinum, gold, or any combination thereof.

### Claim 13 (depends on 9)

The semiconductor device of claim 9, wherein the high-k dielectric material is HfO2, ZrO2, Al2O3, TiO2, La2O3, SrTiO3, LaAlO3, Y2O3, a pervoskite oxide, or any combination thereof.

### Claim 14 (depends on 1)

The semiconductor device of claim 1, wherein the pair of trench contacts have a base that contacts the interfacial layer.

### Claim 15 (depends on 1)

The semiconductor device of claim 1, wherein the interfacial layer comprises at least 99 atomic % boron.

### Claim 16 (depends on 1)

The semiconductor device of claim 1, wherein the interfacial layer comprises boron in an amount in a range from about 1×1022 to about 3×1022 atoms/cm2.

### Claim 17 (depends on 1)

The semiconductor device of claim 1, wherein the interfacial layer comprises 100 atomic % boron.

### Claim 18 (depends on 1)

The semiconductor device of claim 1, wherein the interfacial layer comprises at least 98 atomic % boron.

### Claim 19 (depends on 1)

The semiconductor device of claim 1, wherein the substrate comprises silicon.

### Claim 20 (depends on 1)

The semiconductor device of claim 1, wherein the substrate comprises silicon germanium.