# US 2017/0288031 A1 · Self aligned contact scheme

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2017/0288031 A1
- Document ID: US20170288031A1
- Status: Published application
- Kind: A1
- Application number: 15/407,112
- Filed: 2017-01-16
- Published: 2017-10-05
- Earliest claimed: 2016-04-04
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Tsai-Jung Ho; Kuang-Yuan Hsu; Pei-Ren Jeng
- Web page: https://patentgrep.com/patent/US20170288031A1

## CPC

- H10D 64/259: {Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An embodiment is a method including forming a first gate over a substrate, the first gate having first gate spacers on opposing sidewalls, forming a first hard mask layer over the first gate, forming a second hard mask layer over the first hard mask layer, the second hard mask layer having a different material composition than the first hard mask layer, forming a first dielectric layer adjacent and over the first gate, etching a first opening through the first dielectric layer to expose a portion of the substrate, at least a portion of the second hard mask layer being exposed in the first opening, filling the first opening with a conductive material, and removing the second hard mask layer and the portions of the conductive material and first dielectric layer above the first hard mask layer to form a first conductive contact in the remaining first dielectric layer.

## Claims

### Claim 1

A method comprising:
forming a first gate over a substrate;
forming a first dielectric layer over the substrate and surrounding the first gate;
forming a first hard mask layer over the first gate;
forming a second hard mask layer over the first hard mask layer;
planarizing the second hard mask layer to have a top surface level with a top surface of the first dielectric layer;
forming a second dielectric layer over the first gate and the first dielectric layer;
etching a first opening through the second dielectric layer and the first dielectric layer to expose a portion of the substrate;
filling the first opening with a conductive material; and
recessing the second hard mask layer, the conductive material, and the second dielectric layer to level top surfaces of the first hard mask layer, the conductive material, and the first dielectric layer, the recessed conductive material forming a first conductive contact.

### Claim 2 (depends on 1)

The method of claim 1 further comprising:
first gate spacers on opposing sidewalls of the first gate and the first hard mask layer.

### Claim 3 (depends on 2)

The method of claim 2, wherein the second hard mask layer is on top surfaces of the first gate spacers.

### Claim 4 (depends on 1)

The method of claim 1, wherein the second hard mask layer comprises a metal nitride or a metal oxide.

### Claim 5 (depends on 4)

The method of claim 4, wherein the second hard mask layer comprises TiO, HfO, AlO, ZrO, ZrN, or a combination thereof.

### Claim 6 (depends on 1)

The method of claim 1, wherein forming the first gate over the substrate comprises:
forming a first dummy gate over the substrate, the first dummy gate comprising a first dummy gate dielectric on the substrate and a first dummy gate electrode on the first dummy gate dielectric;
forming first gate spacers on opposing sidewalls of the first dummy gate;
forming source/drain regions in the substrate using the first dummy gate and first gate spacers as a mask;
forming a first etch stop layer over the substrate, the first dummy gate, and the first gate spacers;
forming the first dielectric layer over the first etch stop layer;
planarizing the first dielectric layer to expose a portion of the first dummy gate; and
replacing the first dummy gate with the first gate.

### Claim 7 (depends on 1)

The method of claim 1 further comprising:
recessing the first gate to have a top surface below the top surface the first dielectric layer, the first hard mask layer being formed on the recessed top surface of the first gate; and
recessing the first hard mask layer to have a top surface below the top surface of the first dielectric layer, the second hard mask layer being formed on the recessed top surface of the first hard mask layer.

### Claim 8 (depends on 1)

The method of claim 1 further comprising:
after recessing the second hard mask layer, the conductive material, and the second dielectric layer, forming a third dielectric layer over the first hard mask layer and the first dielectric layer; and
forming a second conductive contact through the third dielectric layer to the first conductive contact.

### Claim 9 (depends on 8)

The method of claim 8, wherein a bottom surface of the second conductive contact contacts a top surface of the first hard mask layer and a top surface of the first conductive contact.

### Claim 10

A method comprising:
forming a first metal gate over a substrate, the first metal gate having first gate spacers on opposing sidewalls of the first metal gate;
forming a first dielectric layer over the substrate and adjacent the first metal gate;
recessing the first metal gate to have a top surface below a top surface of a the first dielectric layer;
forming a first hard mask layer on the recessed top surface of the first metal gate;
recessing the first hard mask layer and the first gate spacers to have top surfaces below the top surface of the first dielectric layer; and
forming a second hard mask layer on the recessed top surfaces of the first hard mask layer and the first gate spacers.

### Claim 11 (depends on 10)

The method of claim 10 further comprising:
planarizing the second hard mask layer to have a top surface level with the top surface of the first dielectric layer.

### Claim 12 (depends on 10)

The method of claim 10, wherein the second hard mask layer comprises a metal nitride or a metal oxide.

### Claim 13 (depends on 10)

The method of claim 10, wherein the first metal gate comprises a high-k gate dielectric layer on the substrate and along inner sidewalls of the first gate spacers and a metal gate electrode on the high-k gate dielectric layer.

### Claim 14 (depends on 10)

The method of claim 10 further comprising:
forming a second dielectric layer over the second hard mask layer and first hard mask layer;
etching a first opening through the second and first dielectric layers to expose a portion of the substrate, at least a portion of the second hard mask layer overlying the first metal gate being exposed in the first opening;
filling the first opening with a conductive material; and
removing the second dielectric layer and the second hard mask layer and the portions of the conductive material and second and first dielectric layer above the first hard mask layer to form a first conductive contact in the first dielectric layer.

### Claim 15 (depends on 14)

The method of claim 14, wherein an entire top surface of the second hard mask layer overlying the first metal gate is exposed in the first opening.

### Claim 16 (depends on 14)

The method of claim 14 further comprising:
after removing the second dielectric layer and the second hard mask layer and the portions of the conductive material and second and first dielectric layer above the first hard mask layer, forming a third dielectric layer over the first hard mask layer and the first dielectric layer; and
forming a second conductive contact through the third dielectric layer to the first conductive contact.

### Claim 17

A method comprising:
forming a first gate and a second gate over a substrate, the first gate and the second gate each having gate spacers on opposing sidewalls of the respective gates;
forming a first dielectric layer over the substrate and surrounding the first gate and the second gate;
forming a first hard mask layer and a second hard mask layer over the first gate and the second gate;
forming a second dielectric layer over the second hard mask layer and the first dielectric layer;
etching a first opening through the second dielectric layer and the first dielectric layer to expose a portion of the substrate adjacent the first gate, at least a portion of the gate spacers on the sidewall of the first gate exposed in the first opening; and
etching a second opening through the second dielectric layer and the first dielectric layer to expose a portion of the substrate adjacent the second gate, the gate spacers on the sidewall of the second gate not being exposed in the second opening.

### Claim 18 (depends on 17)

The method of claim 17 further comprising:
recessing the first gate and the second gate to have top surfaces below a top surface the first dielectric layer, the first hard mask layer being formed on the recessed top surfaces of the first gate and the second gate; and
recessing the first hard mask layer to have a top surface below the top surface of the first dielectric layer, the second hard mask layer being formed on the recessed top surfaces of the first hard mask layer.

### Claim 19 (depends on 18)

The method of claim 18 further comprising:
filling the first opening and second opening with a conductive material; and
removing the second dielectric layer and the second hard mask layer and the portions of the conductive material and first dielectric layer above the first hard mask layer to form a first conductive contact in the remaining first opening and a second conductive contact in the remaining second opening.

### Claim 20 (depends on 19)

The method of claim 19 further comprising:
forming a third dielectric layer over the first hard mask layer and the first dielectric layer; and
forming a third conductive contact through the third dielectric layer to the first conductive contact.