# US 2017/0288018 A1 · Nanowire transistor and method for fabricating the same

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- Number: US 2017/0288018 A1
- Document ID: US20170288018A1
- Status: Published application
- Kind: A1
- Application number: 15/146,898
- Filed: 2016-05-05
- Published: 2017-10-05
- Earliest claimed: 2016-04-01
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Yu-Cheng Tung
- Web page: https://patentgrep.com/patent/US20170288018A1

## CPC

- H10D 62/121: {oriented parallel to substrates}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/0191: {forming stacked channels, e.g. changing their shapes or sizes}
- H10D 30/031: {of thin-film transistors [TFT]}
- H10D 30/0323: {comprising monocrystalline silicon}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/502: {characterised by the stacked channels}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)}
- H10D 30/6744: {Monocrystalline silicon}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/018: {Spacers formed inside holes at the prospective gate locations, e.g. holes left by removing dummy gates}
- H10D 64/668: {the layer being a silicide, e.g. TiSi2}
- H10P 50/642: {Chemical etching}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10D 64/669: {the conductor further comprising additional layers of alloy material, compound material or organic material, e.g. TaN/TiAlN}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method for fabricating a nanowire transistor is disclosed. First, a substrate is provided, and a stack structure is formed on the substrate, in which the stack structure includes a first semiconductor layer and a second semiconductor layer and the first semiconductor layer and the second semiconductor layer are made of different material. Next, a hard mask is formed on the stack structure and a first spacer adjacent to the hard mask, part of the stack structure is removed; a second spacer is formed adjacent to the first spacer and the stack structure; and a source/drain structure is formed adjacent to two sides of the second spacer.

## Claims

### Claim 1

A method for fabricating a nanowire transistor, comprising:
providing a substrate;
forming a stack structure on the substrate, wherein the stack structure comprises a first semiconductor layer and a second semiconductor layer and the first semiconductor layer and the second semiconductor layer comprise different material;
forming a hard mask on the stack structure and a first spacer adjacent to the hard mask;
removing part of the stack structure;
forming a second spacer adjacent to the first spacer and the stack structure, wherein the top surfaces of the first spacer and the second spacer are coplanar; and
forming a source/drain structure adjacent to two sides of the second spacer.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming an interlayer dielectric layer on the source/drain structure and around the second spacer;
removing the hard mask to form a first recess;
removing the first semiconductor layer to form a second recess; and
forming a high-k dielectric layer, a work function metal layer, and a low resistance metal layer in the first recess and the second recess to form a gate structure.

### Claim 3 (depends on 1)

The method of claim 1, wherein the first semiconductor layer and the second semiconductor layer are selected from the group consisting of silicon, germanium, doped silicon, doped germanium, and silicon germanium.

### Claim 4 (depends on 1)

The method of claim 1, wherein the hard mask comprises polysilicon.

### Claim 5 (depends on 1)

The method of claim 1, wherein the first spacer is selected from the group consisting of SiO2, SiN, SiON, and SiCN.

### Claim 6 (depends on 1)

The method of claim 1, wherein the second spacer comprises a metal oxide dielectric material.

### Claim 7 (depends on 1)

The method of claim 1, wherein the source/drain structure comprises an epitaxial material.

### Claim 8 (depends on 1)

The method of claim 1, further comprising:
performing an etching process to remove part of the first semiconductor layer so that a width of the first semiconductor layer is shorter than a width of the second semiconductor layer.

### Claim 9

A nanowire transistor, comprising:
a substrate;
a nanowire channel layer on the substrate;
a gate structure on and around the nanowire channel layer;
a first spacer on the sidewalls of the gate structure;
a second spacer on the sidewalls of the first spacer and the nanowire channel layer, wherein the top surfaces of the first spacer and the second spacer are coplanar; and
a source/drain structure adjacent to two sides of the second spacer.

### Claim 10 (depends on 9)

The nanowire transistor of claim 9, wherein the nanowire channel layer is selected from the group consisting of silicon, germanium, doped silicon, doped germanium, and silicon germanium.

### Claim 11 (depends on 9)

The nanowire transistor of claim 9, further comprising a silicide adjacent to two sides of the gate structure, wherein a bottom of the silicide is lower than a top surface of the nanowire channel layer.

### Claim 12 (depends on 9)

The nanowire transistor of claim 9, wherein the first spacer is selected from the group consisting of SiO2, SiN, SiON, and SiCN.

### Claim 13 (depends on 9)

The nanowire transistor of claim 9, wherein the second spacer comprises a metal oxide dielectric material.

### Claim 14 (depends on 9)

The nanowire transistor of claim 9, wherein the source/drain structure comprises an epitaxial material.

### Claim 15 (depends on 9)

The nanowire transistor of claim 9, wherein the second spacer is between the gate structure and the source/drain structure.

### Claim 16

A nanowire transistor, comprising:
a substrate;
a nanowire channel layer on the substrate;
a gate structure on the nanowire channel layer;
a source/drain structure adjacent to two sides of the gate structure and contacting the substrate directly, wherein the source/drain structure comprises metal and a top surface of the source/drain structure is lower than a top surface of the gate structure; and
a spacer between the nanowire channel layer and the source/drain structure.

### Claim 17 (depends on 16)

The nanowire transistor of claim 16, wherein the nanowire channel layer is selected from the group consisting of silicon, germanium, doped silicon, doped germanium and silicon germanium.

### Claim 18 (depends on 16)

The nanowire transistor of claim 16, further comprising a contact plug electrically connected to the source/drain structure, wherein a top surface of the contact plug is even with a top surface of the gate structure and the contact plug and the source/drain structure comprise same material.

### Claim 19 (depends on 16)

The nanowire transistor of claim 16, further comprising a contact plug electrically connected to the source/drain structure, wherein a top surface of the contact plug is even with a top surface of the gate structure.

### Claim 20 (depends on 16)

The nanowire transistor of claim 16, wherein the spacer comprises a metal oxide dielectric material or a high-k dielectric material.