# US 2017/0288015 A1 · Semiconductor structure including a trench capping layer

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2017/0288015 A1
- Document ID: US20170288015A1
- Status: Published application
- Kind: A1
- Application number: 15/457,384
- Filed: 2017-03-13
- Published: 2017-10-05
- Earliest claimed: 2016-03-31
- Assignees: Globalfoundries Inc.
- Applicants: GLOBALFOUNDRIES Inc.
- Inventors: Elliot John Smith; Steffen Sichler
- Web page: https://patentgrep.com/patent/US20170288015A1

## CPC

- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/01326: {Aspects related to lithography, isolation or planarisation of the conductor}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/671: {the conductor having lateral variation in doping or structure}
- H10D 64/675: {Gate sidewall spacers}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 86/01: Manufacture or treatment
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10P 90/1906: {Preparing SOI wafers}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor structure includes a trench isolation structure and a trench capping layer positioned over the trench isolation structure, wherein the trench isolation layer includes a first electrically insulating material and the trench capping layer includes a second electrically insulating material that is different from the first electrically insulating material. The semiconductor structure also includes a gate structure having a gate insulation layer and a gate electrode positioned over the gate insulation layer, wherein the gate insulation layer includes a high-k material and the gate structure includes a first portion that is positioned over the trench capping layer. A sidewall spacer is positioned adjacent to the gate structure, wherein a portion of the sidewall spacer is positioned on the trench capping layer and contacts the trench capping layer laterally of the gate insulation layer.

## Claims

### Claim 1

A semiconductor structure, comprising:
a trench isolation structure comprising a first electrically insulating material;
a trench capping layer positioned over said trench isolation structure, said trench capping layer comprising a second electrically insulating material that is different from said first electrically insulating material;
a gate structure comprising a gate insulation layer and a gate electrode positioned over said gate insulation layer, wherein said gate insulation layer comprises a high-k material and said gate structure comprises a first portion positioned over said trench capping layer; and
a sidewall spacer positioned adjacent to said gate structure, wherein a portion of said sidewall spacer is positioned on said trench capping layer and contacts said trench capping layer laterally of said gate insulation layer.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, further comprising a support substrate, an electrically insulating layer positioned over said support substrate, and a semiconductor material layer positioned over said electrically insulating layer, wherein said gate structure comprises a second portion that is positioned over a channel region of a field effect transistor, said channel region of said field effect transistor being positioned in said semiconductor material layer.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2, wherein said field effect transistor is one of a plurality of field effect transistors, and wherein said gate structure is a common gate structure of two or more of said plurality of field effect transistors.

### Claim 4 (depends on 2)

The semiconductor structure of claim 2, wherein said field effect transistor further comprises:
a source region provided in said semiconductor material layer adjacent said second portion of said gate structure;
a drain region provided in said semiconductor material layer adjacent said second portion of said gate structure, said source region and said drain region being positioned on opposite sides of said gate structure;
a raised source region positioned over said source region; and
a raised drain region positioned over said drain region.

### Claim 5 (depends on 4)

The semiconductor structure of claim 4, further comprising:
an interlayer dielectric positioned over said raised source region, said raised drain region and said gate structure; and
at least one of a source contact extending through said interlayer dielectric and providing an electrical connection to said raised source region, a drain contact extending through said interlayer dielectric and providing an electrical connection to said raised drain region, and a gate contact extending through said interlayer dielectric and providing an electrical connection to said gate structure.

### Claim 6 (depends on 5)

The semiconductor structure of claim 5, wherein at least one of said source contact and said drain contact extends through said interlayer dielectric and directly contacts a portion of said trench capping layer.

### Claim 7 (depends on 1)

The semiconductor structure of claim 1, wherein said first electrically insulating material comprises silicon dioxide and said second electrically insulating material comprises at least one of silicon nitride, silicon borocarbonitride, and silicon carbonitride.

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, wherein said sidewall spacer comprises at least one of silicon nitride, silicon borocarbonitride, and silicon carbonitride.

### Claim 9 (depends on 1)

The semiconductor structure of claim 1, wherein said trench capping layer does not cover a portion of said trench isolation structure at a side of said sidewall spacer opposite said gate structure.

### Claim 10 (depends on 1)

The semiconductor structure of claim 1, wherein said trench capping layer substantially completely covers said trench isolation structure.

### Claim 11

A semiconductor structure, comprising:
a trench isolation structure positioned in a semiconductor substrate, said trench isolation structure comprising a first insulating material;
a trench capping layer covering at least a portion of an upper surface of said trench isolation structure, said trench capping layer comprising a second insulating material that is different from said first insulating material;
a gate structure comprising a gate insulation layer and a gate electrode positioned above said gate insulation layer, said gate structure having a first portion that is positioned above said trench capping layer and a second portion that is positioned above an active region of a semiconductor material layer of said semiconductor substrate; and
a sidewall spacer positioned adjacent to said gate structure, wherein said sidewall spacer covers a sidewall surface of said gate insulation layer and a portion of an upper surface of said trench capping layer.

### Claim 12 (depends on 11)

The semiconductor structure of claim 11, wherein said gate insulation layer comprises a high-k material.

### Claim 13 (depends on 11)

The semiconductor structure of claim 11, wherein said gate structure further comprises a work function adjustment layer positioned between said gate insulation layer and said gate electrode.

### Claim 14 (depends on 11)

The semiconductor structure of claim 11, wherein said upper surface of said trench capping layer is substantially co-planar with an upper surface of said semiconductor material layer.

### Claim 15 (depends on 11)

The semiconductor structure of claim 11, wherein said trench capping layer covers substantially an entirety of said upper surface of said trench isolation structure.

### Claim 16 (depends on 11)

The semiconductor structure of claim 11, wherein said gate structure is a gate structure of a field effect transistor, the semiconductor structure further comprising a conductive contact element electrically contacting one of a source region and a drain region of said field effect transistor.

### Claim 17 (depends on 16)

The semiconductor structure of claim 16, wherein said conductive contact element directly contacts a portion of said trench capping layer.

### Claim 18 (depends on 11)

The semiconductor structure of claim 11, wherein said first insulating material comprises silicon dioxide and said second insulating material comprises one of silicon nitride, silicon borocarbonitride, and silicon carbonitride.

### Claim 19 (depends on 11)

The semiconductor structure of claim 11, wherein said semiconductor substrate is a silicon-on-insulator (SOI) substrate.

### Claim 20

A semiconductor structure, comprising:
a trench isolation structure positioned in a silicon-on-insulator (SOI) substrate, said trench isolation structure comprising a first insulating material;
a trench capping layer covering at least a portion of an upper surface of said trench isolation structure, wherein said trench capping layer at least partially separates a first active region of a semiconductor material layer of said SOI substrate from a second active region of said semiconductor material layer and comprises a second insulating material that is different from said first insulating material;
a gate structure of a field effect transistor, said gate structure comprising a high-k gate insulation layer positioned above and extending across a first portion of an upper surface of said trench capping layer and a first portion of an upper surface of said semiconductor material layer, a gate electrode positioned above said gate insulation layer, and a work-function adjustment metal layer positioned between said gate insulation layer and said gate electrode;
a sidewall spacer positioned adjacent to said gate structure, wherein said sidewall spacer covers a sidewall surface of said gate insulation layer and a second portion of said upper surface of said trench capping layer;
a raised epitaxial source region positioned above a second portion of said upper surface of said semiconductor material layer;
a raised epitaxial drain region positioned above a third portion of said upper surface of said semiconductor material layer;
an interlayer dielectric covering said gate structure and said raised epitaxial source and drain regions;
a source contact element extending through said interlayer dielectric and electrically contacting said raised epitaxial source region; and
a drain contact element extending through said interlayer dielectric and electrically contacting said raised epitaxial drain region.