# US 2017/0288014 A1 · Semiconductor device and manufacturing method of the same

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- Number: US 2017/0288014 A1
- Document ID: US20170288014A1
- Status: Published application
- Kind: A1
- Application number: 15/516,837
- Filed: 2015-07-22
- Published: 2017-10-05
- Earliest claimed: 2014-12-11
- Assignees: Toyota Jidosha Kabushiki Kaisha
- Applicants: Toyota Jidosha Kabushiki Kaisha
- Inventors: Jun SAITO; Atsushi ONOGI; Sachiko AOI; Shoji MIZUNO
- Web page: https://patentgrep.com/patent/US20170288014A1

## CPC

- H10D 62/109: {Reduced surface field [RESURF] PN junction structures}
- H10D 12/031: {of IGBTs}
- H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/665: {having edge termination structures}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/104: {having particular shapes of the bodies at or near reverse-biased junctions, e.g. having bevels or moats}
- H10D 62/105: {by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] (IGFETs having LDD or drain extension regions H10D30/601)}
- H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions}
- H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)}
- H10D 62/8325: {Silicon carbide}
- H10P 30/20: into semiconductor materials, e.g. for doping
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device may include a semiconductor substrate in which a semiconductor element is provided, and an insulation film provided on the semiconductor substrate, in which the semiconductor substrate may include a first portion and a second portion which has a thickness thinner than a thickness of the first portion, an upper surface of the second portion may be positioned lower than an upper surface of the first portion, a recess extending in a thickness direction of the semiconductor substrate may be provided on the upper surface of the second portion located at a position where the first portion and the second portion adjoin to each other, and the insulation film may extend over from the first portion to the second portion, and fill the recess.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor substrate in which a semiconductor element is provided; and
an insulation film provided on the semiconductor substrate,
wherein
the semiconductor substrate comprises a first portion and a second portion which has a thickness thinner than a thickness of the first portion, wherein an upper surface of the second portion is positioned lower than an upper surface of the first portion,
a recess extending in a thickness direction of the semiconductor substrate is provided on the upper surface of the second portion located at a position where the first portion and the second portion adjoin each other, and
the insulation film extends over from the first portion to the second portion, and fills the recess.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein
a plurality of field limiting rings is provided in the second portion, and
the field limiting ring which is the nearest to the first portion is provided below the recess.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1, wherein
a width of the recess in a direction along which the first portion and the second portion adjoin each other is equal to or less than twice a thickness of the insulation film provided on the upper surface of the second portion.

### Claim 4 (depends on 2)

The semiconductor device according to claim 2, wherein
the field limiting rings are of a first conductivity type,
a trench is provided in an upper surface of the first portion,
a first region of the first conductivity type is provided in a vicinity of a bottom surface of the trench,
a second region of a second conductivity type exists between the field limiting ring which is the nearest to the first portion and the first region,
the bottom surface of the trench is located lower than a bottom surface of the recess, and
a distance from the bottom surface of the trench to the bottom surface of the recess in the thickness direction of the semiconductor substrate is shorter than a distance from the bottom surface of the recess to the upper surface of the second portion.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1, wherein
an angle between a side surface of the recess on a second portion side and a side surface of the first portion is equal to or less than 90 degrees.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1, wherein
an angle between a side surface of the recess on a second portion side and a side surface of the first portion is equal to or less than 45 degrees.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1, wherein
a depth of the recess continuously increases toward the first portion.

### Claim 8

A method of manufacturing a semiconductor device utilizing a semiconductor substrate that comprises a first portion and a second portion which has a thickness thinner than a thickness of the first portion, wherein an upper surface of the second portion is located lower than an upper surface of the first portion,
the method comprising:
forming a recess extending in a thickness direction of the semiconductor substrate on the upper surface of the second portion located at a position where the first portion and the second portion adjoin each other, and
forming, on the semiconductor substrate, an insulation film extending over from the first portion to the second portion and filling the recess.

### Claim 9 (depends on 8)

The method of manufacturing the semiconductor device according to claim 8, further comprising:
forming a field limiting ring below the recess by implanting impurities to the recess.