# US 2017/0288013 A1 · Semiconductor device and method of manufacturing the same

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- Number: US 2017/0288013 A1
- Document ID: US20170288013A1
- Status: Published application
- Kind: A1
- Application number: 15/468,324
- Filed: 2017-03-24
- Published: 2017-10-05
- Earliest claimed: 2016-03-29
- Assignees: Renesas Electronics Corporation
- Applicants: Renesas Electronics Corporation
- Inventors: Shigeo TOKUMITSU
- Web page: https://patentgrep.com/patent/US20170288013A1

## CPC

- H10D 62/40: Crystalline structures
- H10D 62/113: {Isolations within a component, i.e. internal isolations}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/0191: {Manufacturing their doped wells}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/836: {comprising EDMOS}
- H10D 84/856: {the complementary IGFETs having different architectures than each other, e.g. high-voltage and low-voltage CMOS}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/041: {of isolation regions comprising polycrystalline semiconductor materials}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/40: Isolation regions comprising polycrystalline semiconductor materials
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a high voltage transistor formation region defined by an element isolation insulating film, a transistor formation region defined by an element isolation insulating film, and a substrate contact portion. A crystal defect region is formed at a portion of a semiconductor substrate that is positioned immediately below each of the substrate contact portion and element isolation insulating films.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor substrate having a main surface;
a first element formation region defined by a first insulating isolation portion reaching from said main surface to a first depth;
a first semiconductor element formed in said first element formation region;
a second element formation region disposed at a distance from said first element formation region and defined by a second insulating isolation portion reaching from said main surface to said first depth;
a second semiconductor element formed in said second element formation region;
a substrate contact portion formed in a region of said semiconductor substrate that is positioned between said first element formation region and said second element formation region, said substrate contact portion including a portion reaching from said main surface to a second depth; and
a crystal defect region including a first crystal defect region formed at a portion of said semiconductor substrate that is positioned immediately below said substrate contact portion.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein
said crystal defect region includes
a second crystal defect region formed at a portion of said semiconductor substrate that is positioned immediately below said first insulating isolation portion and
a third crystal defect region formed at a portion of said semiconductor substrate that is positioned immediately below said second insulating isolation portion.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2, wherein
said first crystal defect region includes
a first crystal defect region first portion and
a first crystal defect region second portion formed at a position deeper than said first crystal defect region first portion.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1, wherein
said substrate contact portion is disposed so as to surround at least periphery of said first element formation region, and
said first crystal defect region is formed along said substrate contact portion, at a portion of said semiconductor substrate that is positioned immediately below said substrate contact portion.

### Claim 5 (depends on 4)

The semiconductor device according to claim 4, wherein
a plurality of said substrate contact portions are disposed as said substrate contact portion,
a plurality of said substrate contact portions including
a substrate contact first portion and
a substrate contact second portion disposed so as to surround periphery of said substrate contact first portion.

### Claim 6 (depends on 4)

The semiconductor device according to claim 4, wherein
a plurality of said first insulating isolation portions are disposed as said first insulating isolation portion,
a plurality of said first insulating isolation portions including
a first insulating isolation first portion defining said first element formation region and
a first insulating isolation second portion disposed inside said substrate contact portion so as to surround periphery of said first insulating isolation first portion.

### Claim 7 (depends on 4)

The semiconductor device according to claim 4, wherein
a plurality of said first insulating isolation portions are disposed as said first insulating isolation portion,
a plurality of said first insulating isolation portions including
a first insulating isolation first portion defining said first element formation region and
a first insulating isolation second portion disposed so as to surround said first insulating isolation first portion and said substrate contact portion.

### Claim 8

A method of manufacturing a semiconductor device, comprising the steps of:
forming a first isolation groove defining a -first element formation region and a second isolation groove defining a second element formation region to reach from a main surface of a semiconductor substrate to a first depth, and forming an opening reaching from said main surface of said semiconductor substrate positioned between said first isolation groove and said second isolation groove to said first depth;
forming a first semiconductor element in said first element formation region;
forming a second semiconductor element in said second element formation region;
forming an insulating film so as to fill said first isolation groove, said second isolation groove, and said opening to form a first insulating isolation portion in said first isolation groove and form a second insulating isolation portion in said second isolation groove;
successively performing processing on a portion of said insulating film buried in said opening and on said semiconductor substrate to form a contact opening passing through said insulating film to reach said first depth;
forming a conductor in said contact opening to form a substrate contact portion; and
injecting an injection seed not concerned with a conductivity type to form a crystal defect region in said semiconductor substrate,
the step of forming said crystal defect region including the step of forming a first crystal defect region at a portion of said semiconductor substrate that is positioned immediately below said substrate contact portion.

### Claim 9 (depends on 8)

The method of manufacturing a semiconductor device according to claim 8, wherein
the step of forming said crystal defect region includes the step of injecting a first impurity as said injection seed from said first isolation groove, said second isolation groove, and said opening to form a second crystal defect region at a portion of said semiconductor substrate that is positioned immediately below said first isolation groove, form a third crystal defect region at a portion of said semiconductor substrate that is positioned immediately below said second isolation groove, and form said first crystal defect region at a portion of said semiconductor substrate that is positioned at a bottom of said opening.

### Claim 10 (depends on 9)

The method of manufacturing a semiconductor device according to claim 9, wherein
the step of forming said crystal defect region includes the step of injecting a second impurity as said injection seed from said contact opening to form a fourth crystal defect region at a position deeper than said first crystal defect region immediately below a bottom of said contact opening.

### Claim 11 (depends on 8)

The method of manufacturing a semiconductor device according to claim 8, wherein
the step of forming said crystal defect region includes the step of injecting a third impurity as said injection seed from said contact opening to form said first crystal defect region at a portion of said semiconductor substrate that is positioned immediately below a bottom of said contact opening.

### Claim 12 (depends on 8)

The method of manufacturing a semiconductor device according to claim 8, wherein
said injection seed includes at least any one of carbon, silicon, germanium, and argon.