# US 2017/0287974 A1 · Method of manufacturing solid-state image sensor

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- Number: US 2017/0287974 A1
- Document ID: US20170287974A1
- Status: Published application
- Kind: A1
- Application number: 15/455,343
- Filed: 2017-03-10
- Published: 2017-10-05
- Earliest claimed: 2016-03-31
- Assignees: Canon Kabushiki Kaisha
- Applicants: Canon Kabushiki Kaisha
- Inventors: Masashi Kusukawa
- Web page: https://patentgrep.com/patent/US20170287974A1

## CPC

- H10F 39/014: {of CMOS image sensors}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10F 39/80373: {characterised by the gate of the transistor}
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of manufacturing a solid-state image sensor is provided. The method comprises: depositing a gate electrode film above the semiconductor layer; etching the gate electrode film to form a first gate electrode patterned in a pixel region, leaving the gate electrode film in a peripheral region; depositing a first insulating film above the semiconductor layer after the forming the first gate electrode; removing the first insulating film formed in the peripheral region; etching the gate electrode film left in the peripheral region to form a second gate electrode patterned in the peripheral region after the removing the first insulating film; forming a second insulating film above the semiconductor layer after the forming the second gate electrode; and forming a side wall on side surface of the second gate electrode by etching the second insulating film.

## Claims

### Claim 1

A method of manufacturing a solid-state image sensor with a pixel region and a peripheral circuit region being arranged in a semiconductor layer, the method comprising:
depositing a gate electrode film above the semiconductor layer;
etching the gate electrode film to form a first gate electrode patterned in the pixel region, leaving the gate electrode film in the peripheral circuit region;
depositing a first insulating film above the semiconductor layer after the forming the first gate electrode;
removing the first insulating film formed in the peripheral circuit region;
etching the gate electrode film left in the peripheral circuit region to form a second gate electrode patterned in the peripheral circuit region after the removing the first insulating film;
forming a second insulating film above the semiconductor layer after the forming the second gate electrode; and
forming a side wall on side surface of the second gate electrode by etching the second insulating film.

### Claim 2 (depends on 1)

The method according to claim 1, wherein the first insulating film contains an insulator different from the side wall.

### Claim 3 (depends on 1)

The method according to claim 1, wherein a hydrogen concentration of the first insulating film is higher than a hydrogen concentration of the side wall.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the side wall contain silicon oxide.

### Claim 5 (depends on 1)

The method according to claim 1, wherein the first insulating film includes a silicon nitride film.

### Claim 6 (depends on 5)

The method according to claim 5, wherein the first insulating film has a stacked structure including the silicon nitride film and a silicon oxide film.

### Claim 7 (depends on 6)

The method according to claim 6, wherein the first insulating film is stacked in an order of the silicon oxide film and the silicon nitride film from a side of the semiconductor layer, and
the etching the first insulating film includes isotropic dry etching the silicon nitride film and wet etching the silicon oxide film after etching the silicon nitride film.

### Claim 8 (depends on 5)

The method according to claim 5, wherein the silicon nitride film is formed by using a material that contains at least one material selected from the group consisting of dichlorosilane and hexachlorodisilane.

### Claim 9 (depends on 1)

The method according to claim 1, wherein in the forming the second gate electrode, the pixel region is covered with a mask pattern.

### Claim 10 (depends on 1)

The method according to claim 1, further comprising:
forming source/drain regions in portions of the semiconductor layer adjacent to the second gate electrode after the forming the second gate electrode; and
forming metal silicide on surfaces of the second gate electrode and the source/drain regions.