# US 2017/0287952 A1 · Array substrate, display panel and display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0287952 A1 - Document ID: US20170287952A1 - Status: Published application - Kind: A1 - Application number: 15/513,743 - Filed: 2016-03-14 - Published: 2017-10-05 - Earliest claimed: 2015-04-13 - Assignees: Boe Technology Group Co., Ltd. - Applicants: Boe Technology Group Co., Ltd. - Inventors: Guang LI; Libin LIU - Web page: https://patentgrep.com/patent/US20170287952A1 ## CPC - H10D 86/60: wherein the TFTs are in active matrices - H10D 86/441: {Interconnections, e.g. scanning lines} - H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors} - G02F 1/133345: {Insulating layers (G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence)} - G02F 1/134309: {characterised by their geometrical arrangement} - G02F 1/13454: {Drivers integrated on the active matrix substrate (G02F1/136277 takes precedence)} - G02F 1/136286: {Wiring, e.g. gate line, drain line} - G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} - G09G 3/3225: using an active matrix - G09G 3/3266: Details of drivers for scan electrodes - G09G 3/3677: {suitable for active matrices only} - G09G 2300/0408: Integration of the drivers onto the display substrate - G09G 2300/0426: Layout of electrodes and connections - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract An array substrate, a display panel and a display device are provided. The array substrate comprises: an active area, a package area and a drive circuit area, wherein the drive circuit area is located between the active area and the package area. A package metal layer is provided at the package area, and at least one groove structure is provided on a side of the package metal layer in a proximity to the drive circuit area. At least one drive unit is provided at the drive circuit area and comprises at least one element, wherein the element is provided in the groove structure. ## Claims ### Claim 1 An array substrate, comprising: an active area, a package area and a driving circuit area, the driving circuit area being located between the active area and the package area; a packaging metal layer, arranged in the package area, and a side of the packaging metal layer facing to the driving circuit area being provided with at least one groove structure; at least one driving unit, arranged in the driving circuit region and comprising at least one element; wherein, the element is arranged in the groove structure. ### Claim 2 (depends on 1) The array substrate according to claim 1, wherein, the element is of a capacitive structure. ### Claim 3 (depends on 2) The array substrate according to claim 2, wherein, one groove structure accommodates one capacitive structure. ### Claim 4 (depends on 2) The array substrate according to claim 2, wherein, the array substrate further comprises an insulating layer; in a direction perpendicular to a plate surface of the array substrate, the capacitive structure includes: a first electrode and a second electrode which are oppositely arranged and insulated; the insulating layer is at least located between the first electrode and the second electrode; the packaging metal layer is arranged on a same layer as the first electrode or the second electrode. ### Claim 5 (depends on 2) The array substrate according to claim 2, wherein, the driving unit further includes: at least one thin film transistor; the first electrode is arranged on a same layer as a gate metal layer or a source and drain metal layer of the thin film transistor; the second electrode is arranged on a same layer as the source and drain metal layer or the gate metal layer of the thin film transistor. ### Claim 6 (depends on 1) The array substrate according to claim 1, wherein, the driving circuit area includes a gate driving circuit area; and the driving unit includes a gate driving unit located in the gate driving circuit area. ### Claim 7 (depends on 6) The array substrate according to claim 6, wherein, the gate driving circuit area is located on one or two sides of the active area in a gate line direction. ### Claim 8 (depends on 1) The array substrate according to claim 1, wherein, the array substrate further comprises: sealant located on the packaging metal layer. ### Claim 9 (depends on 1) The array substrate according to claim 1, wherein, the active area further includes a plurality of pixel units, each pixel unit includes a thin film transistor, and the first electrode is arranged on a same layer as a gate metal layer or a source and drain metal layer of the thin film transistor; the second electrode is arranged on a same layer as the source and drain metal layer or the gate metal layer of the thin film transistor. ### Claim 10 (depends on 1) A display panel, comprising the array substrate according to claim 1. ### Claim 11 (depends on 10) A display device, comprising the display panel according to claim 10. ### Claim 12 (depends on 3) The array substrate according to claim 3, wherein, the array substrate further comprises an insulating layer; in a direction perpendicular to a plate surface of the array substrate, the capacitive structure includes: a first electrode and a second electrode which are oppositely arranged and insulated; the insulating layer is at least located between the first electrode and the second electrode; the packaging metal layer is arranged on a same layer as the first electrode or the second electrode. ### Claim 13 (depends on 3) The array substrate according to claim 3, wherein, the driving unit further includes: at least one thin film transistor; the first electrode is arranged on a same layer as a gate metal layer or a source and drain metal layer of the thin film transistor; the second electrode is arranged on a same layer as the source and drain metal layer or the gate metal layer of the thin film transistor. ### Claim 14 (depends on 2) The array substrate according to claim 2, wherein, the driving circuit area includes a gate driving circuit area; and the driving unit includes a gate driving unit located in the gate driving circuit area. ### Claim 15 (depends on 3) The array substrate according to claim 3, wherein, the driving circuit area includes a gate driving circuit area; and the driving unit includes a gate driving unit located in the gate driving circuit area. ### Claim 16 (depends on 2) The array substrate according to claim 2, wherein, the array substrate further comprises: sealant located on the packaging metal layer. ### Claim 17 (depends on 3) The array substrate according to claim 3, wherein, the array substrate further comprises: sealant located on the packaging metal layer. ### Claim 18 (depends on 2) The array substrate according to claim 2, wherein, the active area further includes a plurality of pixel units, each pixel unit includes a thin film transistor, and the first electrode is arranged on a same layer as a gate metal layer or a source and drain metal layer of the thin film transistor; the second electrode is arranged on a same layer as the source and drain metal layer or the gate metal layer of the thin film transistor. ### Claim 19 (depends on 3) The array substrate according to claim 3, wherein, the active area further includes a plurality of pixel units, each pixel unit includes a thin film transistor, and the first electrode is arranged on a same layer as a gate metal layer or a source and drain metal layer of the thin film transistor; the second electrode is arranged on a same layer as the source and drain metal layer or the gate metal layer of the thin film transistor.