# US 2017/0287947 A1 · Array substrate and fabrication method, display panel, and display device

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 2017/0287947 A1
- Document ID: US20170287947A1
- Status: Published application
- Kind: A1
- Application number: 15/186,869
- Filed: 2016-06-20
- Published: 2017-10-05
- Earliest claimed: 2016-03-31
- Assignees: Shanghai Tianma Am-Oled Co., Ltd.; Tianma Micro-Electronics Co., Ltd.
- Applicants: Shanghai Tianma AM-OLED Co., Ltd.; Tianma Micro-electronics Co., Ltd.
- Inventors: QI LI; DONG QIAN; DUZEN PENG
- Web page: https://patentgrep.com/patent/US20170287947A1

## CPC

- H10D 86/60: wherein the TFTs are in active matrices
- G02F 1/133514: {Colour filters}
- G02F 1/136227: {Through-hole connection of the pixel electrode to the active element through an insulation layer}
- H10D 30/6731: {Top-gate only TFTs}
- H10D 30/6745: {Polycrystalline or microcrystalline silicon}
- H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies}
- H10D 86/0231: {using masks, e.g. half-tone masks}
- H10D 86/421: {having a particular composition, shape or crystalline structure of the active layer}
- H10D 86/443: {adapted for preventing breakage, peeling or short circuiting}
- H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors}
- G02F 1/13685: {Top gates}
- H10K 59/1213: {the pixel elements being TFTs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES

## Abstract

The present disclosure provides an array substrate, including a substrate, a first functional layer configured on one side of the substrate, a first insulating layer configured on the first functional layer facing away from the substrate, a second functional layer configured on the first insulating layer facing away from the substrate, a second insulating layer configured on the second functional layer facing away from the substrate, a third functional layer configured on the second insulating layer facing away from the substrate, a third insulating layer configured on the third functional layer facing away from the substrate, a fourth functional layer configured on the third insulating layer facing away from the substrate, and a plurality of through-holes configured to electrically connect different functional layers, wherein the depth of any through-holes does not exceed the thickness of two adjacent insulating layers.

## Claims

### Claim 1

An array substrate, comprising:
a substrate;
a first functional layer configured on one side of the substrate;
a first insulating layer configured on the first functional layer facing away from the substrate;
a second functional layer configured on the first insulating layer facing away from the substrate;
a second insulating layer configured on the second functional layer facing away from the substrate;
a third functional layer configured on the second insulating layer facing away from the substrate;
a third insulating layer configured on the third functional layer facing away from the substrate;
a fourth functional layer configured on the third insulating layer facing away from the substrate; and
a plurality of through-holes configured to electrically connect different functional layers, wherein the depth of any through-holes does not exceed the thickness of two adjacent insulating layers.

### Claim 2 (depends on 1)

The array substrate of claim 1, wherein:
the functional layers and the insulating layers are single layer structures or multi-layer structures including a plurality of sub-layers.

### Claim 3 (depends on 1)

The array substrate of claim 1, wherein:
the first functional layer is made of semiconductor material; and
the second functional layer, the third functional layer, and the fourth functional layer are made of metal.

### Claim 4 (depends on 1)

The array substrate of claim 1, wherein:
orthogonal projection centers of any two through-holes on the substrate do not coincide with each other.

### Claim 5 (depends on 1)

The array substrate of claim 1, wherein:
the first insulating layer has a thickness of approximately 100 nm to 200 nm;
the second insulating layer has a thickness of approximately 50 nm to 150 nm; and
the third insulating layer has a thickness of approximately 200 nm to 700 nm.

### Claim 6 (depends on 1)

The array substrate of claim 1, further including a first transistor, wherein:
a semiconductor layer of the first transistor is located in the first functional layer;
a gate electrode of the first transistor is located in the second functional layer; and
a source electrode and a drain electrode of the first transistor are located in the fourth functional layer.

### Claim 7 (depends on 6)

The array substrate of claim 6, wherein:
the third functional layer includes a first conductive portion and a second conductive portion;
the through-holes include a first through-hole and a second through-hole that penetrate the first insulating layer and the second insulating layer, and a third through-hole and a fourth through-hole that penetrate the third insulating layer;
the drain electrode of the first transistor is electrically connected to the first conductive portion by the third through-hole while the first conductive portion is electrically connected to the semiconductor layer of the first transistor by the first through-hole; and
the drain electrode of the first transistor is electrically connected to the second conductive portion by the fourth through-hole while the second conductive portion is electrically connected to the semiconductor layer of the first transistor by the second through-hole.

### Claim 8 (depends on 7)

The array substrate of claim 7, further including a first capacitor and a fifth through-hole, wherein:
the fifth through-hole penetrates the second insulating layer and the third insulating layer;
a first electrode of the first capacitor is located in the second functional layer;
a second electrode of the first capacitor is located in the third functional layer; and
the first electrode of the first capacitor is electrically connected to the drain electrode or the source electrode of the first transistor by the fifth through-hole.

### Claim 9 (depends on 8)

The array substrate of claim 8, further including a sixth through-hole and a third conductive portion, wherein:
the sixth through-hole penetrates the third insulating layer;
the third conductive portion is located in the fourth functional layer; and
the second electrode of the first capacitor is electrically connected to the third conductive portion by the sixth through-hole.

### Claim 10 (depends on 8)

The array substrate of claim 8, further including a seventh through-hole and a fourth conductive portion, wherein:
the seventh through-hole penetrates the second insulating layer;
the fourth conductive portion is located in the third functional layer; and
the first electrode of the first capacitor is electrically connected to the fourth conductive portion by the seventh through-hole.

### Claim 11 (depends on 7)

The array substrate of claim 7, further including a second transistor and an eighth through-hole, wherein:
the eighth through-hole penetrates the second insulating layer and the third insulating layer;
a semiconductor layer of the second transistor is located in the first functional layer;
a gate electrode of the second transistor is located in the second functional layer;
a source electrode and a drain electrode of the second transistor are located in the fourth functional layer; and
the source electrode or the drain electrode of the first transistor is electrically connected to the gate electrode of the second transistor by the eighth through-hole.

### Claim 12 (depends on 7)

The array substrate of claim 7, further including a third transistor, wherein:
a semiconductor layer of the third transistor is located in the first functional layer;
a gate electrode of the third transistor is located in the second functional layer; and
a source electrode and a drain electrode of the third transistor are located in the third functional layer.

### Claim 13 (depends on 12)

The array substrate of claim 12, further including a ninth through-hole, wherein:
the ninth through-hole penetrates the second insulating layer and the third insulating layer; and
the source electrode or the drain electrode of the first transistor is electrically connected to the gate electrode of the third transistor by the ninth through-hole.

### Claim 14 (depends on 12)

The array substrate of claim 12, further including a tenth through-hole and a fifth conductive portion, wherein:
the tenth through-hole penetrates the third insulating layer;
the fifth conductive portion is located in the fourth functional layer; and
the source electrode or the drain electrode of the third transistor is electrically connected to the fifth conductive portion by the tenth through-hole.

### Claim 15 (depends on 12)

The array substrate of claim 12, further including an eleventh through-hole and a sixth conductive portion, wherein:
the eleventh through-hole penetrates the second insulating layer;
the sixth conductive portion is located in the second functional layer; and
the source electrode or the drain electrode of the third transistor is electrically connected to the sixth conductive portion by the eleventh through-hole.

### Claim 16

A method of fabricating the array substrate, comprising:
providing a substrate;
depositing a graphic pattern of a first functional layer on the substrate;
depositing a first insulating layer on the first functional layer;
depositing a graphic pattern of a second functional layer on the first insulating layer;
depositing a second insulating layer on the second functional layer;
etching the first and second insulating layers to form a plurality of first-type through-holes that penetrate the first and second insulating layers;
depositing a graphic pattern of a third functional layer on the second insulating layer, and electrically connecting at least a portion of the third functional layer to at least a portion of the first functional layer by the first-type through-holes;
depositing a third insulating layer on the third functional layer;
etching the third insulating layer to form a plurality of second-type through-holes that penetrate the third insulating layer; and
depositing a graphic pattern of a fourth functional layer on the third insulating layer, and electrically connecting at least a portion of the third functional layer to at least a portion of the fourth functional layer by the second-type through-holes.

### Claim 17 (depends on 16)

The method of fabricating the array substrate of claim 16, further including:
while etching the third insulating layer to form the plurality of second-type through-holes that penetrate the third insulating layer, etching the second and third insulating layers to form a plurality of third-type through-holes that penetrate the second and third insulating layers, and electrically connecting at least a portion of the fourth functional layer to at least a portion of the second functional layer by the third-type through-holes.

### Claim 18 (depends on 16)

The method of fabricating the array substrate of claim 16, further including:
while etching the first and second insulating layers to form the plurality of first-type through-holes that penetrate the first and second insulating layers, etching the second insulating layer to form a plurality of fourth-type through-holes that penetrate the second insulating layer, and electrically connecting at least a portion of the third functional layer to at least a portion of the second functional layer by the fourth-type through-holes.

### Claim 19

A display panel, comprising an array substrate and a light emitting functional layer located on the array substrate, wherein the array substrate comprising:
a substrate;
a first functional layer configured on one side of the substrate;
a first insulating layer configured on the first functional layer facing away from the substrate;
a second functional layer configured on the first insulating layer facing away from the substrate;
a second insulating layer configured on the second functional layer facing away from the substrate;
a third functional layer configured on the second insulating layer facing away from the substrate;
a third insulating layer configured on the third functional layer facing away from the substrate;
a fourth functional layer configured on the third insulating layer facing away from the substrate; and
a plurality of through-holes configured to electrically connect different functional layers, wherein the depth of any through-holes does not exceed the thickness of two adjacent insulating layers.

### Claim 20

A display device, comprising a display panel which includes an array substrate and a light emitting functional layer located on the array substrate, wherein the array substrate comprising:
a substrate;
a first functional layer configured on one side of the substrate;
a first insulating layer configured on the first functional layer facing away from the substrate;
a second functional layer configured on the first insulating layer facing away from the substrate;
a second insulating layer configured on the second functional layer facing away from the substrate;
a third functional layer configured on the second insulating layer facing away from the substrate;
a third insulating layer configured on the third functional layer facing away from the substrate;
a fourth functional layer configured on the third insulating layer facing away from the substrate; and
a plurality of through-holes configured to electrically connect different functional layers, wherein the depth of any through-holes does not exceed the thickness of two adjacent insulating layers.