# US 2017/0287943 A1 · High aperture ratio display by introducing transparent storage capacitor and via hole > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0287943 A1 - Document ID: US20170287943A1 - Status: Published application - Kind: A1 - Application number: 15/136,785 - Filed: 2016-04-22 - Published: 2017-10-05 - Earliest claimed: 2016-03-31 - Assignees: QUALCOMM Incorporated - Applicants: Qualcomm Incorporated - Inventors: Jia Wei Ma; Wei Hsiang Weng; Jan Bos; Cheonhong Kim - Web page: https://patentgrep.com/patent/US20170287943A1 ## CPC - H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies} - G09G 3/2092: {Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto (suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165)} - H10D 1/692: {Electrodes} - H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate} - H10D 62/80: characterised by the materials - H10D 62/86: being Group II-VI materials, e.g. ZnO - H10D 64/512: {Disposition of the gate electrodes, e.g. buried gates} - H10D 86/411: {characterised by materials, geometry or structure of the substrates} - H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO} - H10D 86/441: {Interconnections, e.g. scanning lines} - H10D 86/481: {integrated with passive devices, e.g. auxiliary capacitors} - H10D 86/60: wherein the TFTs are in active matrices - H10D 99/00: Subject matter not provided for in other groups of this subclass - H10P 14/3426: {Oxides} - H10P 14/3434: {being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424)} - H10P 14/38: {characterised by treatments done after the formation of the materials} - H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass - H10P 95/90: Thermal treatments, e.g. annealing or sintering - G09G 2300/08: Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements - G09G 2310/0264: Details of driving circuits - G09G 2330/028: Generation of voltages supplied to electrode drivers in a matrix display other than LCD - H10D 62/875: {being semiconductor metal oxide, e.g. InGaZnO (Group II-VI materials H10D62/86; Group I-VI materials H10D62/871; Pb compounds or alloys H10D62/874)} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract This disclosure provides apparatuses and methods of manufacturing apparatuses including thin film transistors (TFTs) and storage capacitors. An apparatus can include a substrate, a TFT, a storage capacitor adjacent to the TFT, and a common electrode. The storage capacitor can be substantially transparent to increase aperture ratio of a display device. The storage capacitor can include an insulating layer between a first transparent electrode and a second transparent electrode. The TFT can include a gate electrode, a gate insulating layer, an oxide semiconductor, source and drain electrodes, and a dielectric layer. The oxide semiconductor can be formed out of the same layer as the first transparent electrode, and the common electrode can be formed out of the same layer as the oxide semiconductor or the source and drain electrodes. ## Claims ### Claim 1 An apparatus comprising: (i) a substrate; (ii) a thin film transistor (TFT) including: a gate electrode over the substrate; an oxide semiconductor layer, wherein the oxide semiconductor layer has a channel region between a source region and a drain region; a first insulating layer between the gate electrode and the oxide semiconductor layer; a source electrode on a source region of the oxide semiconductor layer; a drain electrode on a drain region of the oxide semiconductor layer; and a dielectric layer over the channel region of the oxide semiconductor layer; (iii) a storage capacitor adjacent to the TFT and including: a first transparent electrode over the substrate, wherein the first transparent electrode has a substantially similar thickness and composition as the oxide semiconductor layer; a second transparent electrode over the first transparent electrode and at least partially overlapping with the first transparent electrode; and a second insulating layer between the first transparent electrode and the second transparent electrode; and (iv) a common electrode, wherein the common electrode is electrically connected to the first transparent electrode. ### Claim 2 (depends on 1) The apparatus of claim 1, wherein the common electrode has a substantially similar thickness and composition as the source and drain electrodes. ### Claim 3 (depends on 1) The apparatus of claim 1, wherein the common electrode has a substantially similar thickness and composition as the oxide semiconductor layer. ### Claim 4 (depends on 1) The apparatus of claim 1, wherein the second transparent electrode is electrically connected to the oxide semiconductor layer by a transparent via. ### Claim 5 (depends on 1) The apparatus of claim 1, wherein the second transparent electrode is electrically connected to the drain electrode by a transparent via. ### Claim 6 (depends on 1) The apparatus of claim 1, wherein the oxide semiconductor layer and the first transparent electrode include at least one of indium-gallium-zinc-oxide (IGZO), indium-zinc-tin-oxide (IZTO), zinc oxide (ZnO), indium-zinc-oxide (IZO), indium oxide (InO), and tin oxide (SnO). ### Claim 7 (depends on 1) The apparatus of claim 1, wherein the second transparent electrode includes at least one of indium-tin-oxide (ITO), indium-zinc-oxide (IZO), and aluminum-doped zinc oxide (AZO). ### Claim 8 (depends on 1) The apparatus of claim 1, wherein the first transparent electrode and the oxide semiconductor layer share a first common thin film layer, and wherein the common electrode and the source and drain electrodes share a second common thin film layer. ### Claim 9 (depends on 1) The apparatus of claim 1, wherein the first transparent electrode, the oxide semiconductor layer, and the common electrode share a common thin film layer. ### Claim 10 (depends on 1) The apparatus of claim 1, wherein the first transparent electrode is directly connected to the common electrode and is not electrically connected to the source and drain electrodes. ### Claim 11 (depends on 1) The apparatus of claim 1, wherein the first transparent electrode has a lower electrical resistance than the oxide semiconductor layer in the channel region. ### Claim 12 (depends on 1) The apparatus of claim 1, wherein the drain region of the oxide semiconductor layer have a lower electrical resistance than the oxide semiconductor layer in the channel region. ### Claim 13 (depends on 1) The apparatus of claim 1, wherein the substrate includes at least one of glass, polyethylene terephthalate (PET), and polyethylene naphthalate (PEN). ### Claim 14 (depends on 1) The apparatus of claim 1, wherein the storage capacitor and the substrate are substantially transparent to visible light, and wherein the gate electrode is substantially non-transparent to ultraviolet and visible light. ### Claim 15 (depends on 1) The apparatus of claim 1, wherein the dielectric layer and the second insulating layer share a common thin film layer. ### Claim 16 (depends on 1) The apparatus of claim 1, further comprising: an etch stop layer on the oxide semiconductor layer, wherein the etch stop layer is between the oxide semiconductor layer and the dielectric layer. ### Claim 17 (depends on 1) The apparatus of claim 1, further comprising: a plurality of display elements, wherein the common electrode is configured to apply a common voltage to each of the plurality of display elements, the apparatus being a display device comprising the plurality of display elements. ### Claim 18 (depends on 17) The apparatus of claim 17, further comprising: a processor that is configured to communicate with one or more display elements, the processor being configured to process image data; and a memory device that is configured to communicate with the processor. ### Claim 19 (depends on 18) The apparatus of claim 18, further comprising: a driver circuit configured to send at least one signal to one or more display elements; and a controller configured to send at least a portion of the image data to the driver circuit. ### Claim 20 (depends on 18) The apparatus of claim 18, further comprising: an image source module configured to send the image data to the processor, wherein the image source module comprises at least one of a receiver, transceiver, and transmitter. ### Claim 21 (depends on 18) The apparatus of claim 18, further comprising: an input device configured to receive input data and to communicate the input data to the processor. ### Claim 22 A method of manufacturing an apparatus, the apparatus having a TFT region and a storage capacitor region adjacent to the TFT region, the method comprising: providing a substrate in the TFT and the storage capacitor region; forming a first metal layer on the substrate in the TFT region; forming a first dielectric layer on the first metal layer; forming an oxide semiconductor layer in the storage capacitor region and on the first dielectric layer in the TFT region, wherein the oxide semiconductor layer in the TFT region has a channel region between a source region and a drain region; forming a second metal layer on the oxide semiconductor layer, the second metal layer in contact with the source region and the drain region, and the second metal layer in contact with a portion of the oxide semiconductor layer in the storage capacitor region; forming a second dielectric layer on the second metal layer and the oxide semiconductor layer in the TFT region; forming a transparent conductive layer over the oxide semiconductor layer in the storage capacitor region, the transparent conductive layer at least partially overlapping with the oxide semiconductor layer in the storage capacitor region; and applying, after any operation subsequent to forming the oxide semiconductor layer, a resistance lowering process to the oxide semiconductor layer in the storage capacitor region so that the oxide semiconductor layer in the storage capacitor region has a lower electrical resistance than the oxide semiconductor layer in the channel region. ### Claim 23 (depends on 22) The method of claim 22, wherein applying the resistance lowering process includes exposing at least a portion of the oxide semiconductor layer to ultraviolet light. ### Claim 24 (depends on 22) The method of claim 22, wherein applying the resistance lowering process includes treating at least a portion of the oxide semiconductor layer with plasma prior to forming the second dielectric layer. ### Claim 25 (depends on 22) The method of claim 22, wherein the transparent conductive layer is electrically connected to the second metal layer or the oxide semiconductor layer by a transparent via. ### Claim 26 (depends on 22) The method of claim 22, wherein the oxide semiconductor layer includes at least one of IGZO, IZTO, ZnO, IZO, InO, and SnO, and the transparent conductive layer includes at least one of ITO, IZO, and AZO. ### Claim 27 (depends on 22) The method of claim 22, wherein the second metal layer contacting the portion of the oxide semiconductor layer in the storage capacitor region is a common electrode. ### Claim 28 A method of manufacturing an apparatus, the apparatus having a TFT region, a storage capacitor region adjacent to the TFT region, and a common electrode region adjacent to the storage capacitor region, the method comprising: providing a substrate in the TFT, the storage capacitor, and the common electrode region; forming a first metal layer on the substrate in the TFT region; forming a first dielectric layer on the first metal layer; forming an oxide semiconductor layer in the storage capacitor region and the common electrode region and on the first dielectric layer in the TFT region, wherein the oxide semiconductor layer in the TFT region has a channel region between a source region and a drain region; forming a second metal layer on the oxide semiconductor layer, the second metal layer in contact with the source region and the drain region; forming a second dielectric layer on the second metal layer and the oxide semiconductor layer in the TFT region; forming a transparent conductive layer over the oxide semiconductor layer in the storage capacitor region, the transparent conductive layer at least partially overlapping with the oxide semiconductor layer in the storage capacitor region; and applying, after any operation subsequent to forming the oxide semiconductor layer, a resistance lowering process to the oxide semiconductor layer in the storage capacitor region and the common electrode region so that the oxide semiconductor layer in the storage capacitor region and the common electrode region has a lower electrical resistance than the oxide semiconductor layer in the TFT region. ### Claim 29 (depends on 28) The method of claim 28, wherein applying the resistance lowering process includes exposing at least a portion of the oxide semiconductor layer to ultraviolet light. ### Claim 30 (depends on 28) The method of claim 28, wherein applying the resistance lowering process includes treating at least a portion of the oxide semiconductor layer with plasma prior to forming the second dielectric layer. ### Claim 31 (depends on 28) The method of claim 28, wherein the transparent conductive layer is electrically connected to the second metal layer or the oxide semiconductor layer by a transparent via. ### Claim 32 (depends on 28) The method of claim 28, wherein the oxide semiconductor layer includes at least one of IGZO, IZTO, ZnO, IZO, InO, and SnO, and the transparent conductive layer includes at least one of ITO, IZO, and AZO.