# US 2017/0287928 A1 · Semiconductor memory devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0287928 A1 - Document ID: US20170287928A1 - Status: Published application - Kind: A1 - Application number: 15/430,879 - Filed: 2017-02-13 - Published: 2017-10-05 - Earliest claimed: 2016-04-04 - Inventors: Kohji KANAMORI; Shinhwan KANG; Kwang-Soo KIM; Youngwoo PARK; Chadong YEO; Jaegoo LEE - Web page: https://patentgrep.com/patent/US20170287928A1 ## CPC - H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels - G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay} - H10B 43/10: characterised by the top-view layout - H10W 20/43: Layouts of interconnections - H10B: ELECTRONIC MEMORY DEVICES - G11C: STATIC STORES (semiconductor memory devices H10B) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Semiconductor devices are provided. Semiconductor devices may include a stack structure including word lines stacked on a substrate, first vertical pillars and second vertical pillars that extend through the stack structure, a first string select line overlapping the first vertical pillars in a plan view, and a second string select line overlapping the second vertical pillars in the plan view and being spaced apart from the first string select line in a first direction. In a plan view, a shortest distance between a side of one of the first vertical pillars and a side of one of the second vertical pillars is less than a shortest distance between a side of the first string select line and a side of the second string select line. ## Claims ### Claim 1 A semiconductor memory device comprising: a stack structure including a plurality of word lines stacked on a substrate; a plurality of first vertical pillars and a plurality of second vertical pillars that extend through the stack structure; a first string select line overlapping the plurality of first vertical pillars in a plan view; and a second string select line overlapping the plurality of second vertical pillars in the plan view and being spaced apart from the first string select line in a first direction, wherein, in the plan view, a shortest distance between a side of one of the plurality of first vertical pillars and a side of one of the plurality of second vertical pillars that is closest to the one of the plurality of first vertical pillars is less than a shortest distance between a side of the first string select line and a side of the second string select line. ### Claim 2 (depends on 1) The semiconductor memory device of claim 1, further comprising: a plurality of first string channel pillars that extend through the first string select line and are electrically connected to the plurality of first vertical pillars, respectively; and a plurality of second string channel pillars that extend through the second string select line and are electrically connected to the plurality of second vertical pillars, respectively. ### Claim 3 (depends on 2) The semiconductor memory device of claim 2, wherein the plurality of first vertical pillars has a diameter that is greater than a diameter of the plurality of first string channel pillars, and wherein the plurality of second vertical pillars has a diameter that is greater than a diameter of the plurality of second string channel pillars. ### Claim 4 (depends on 2) The semiconductor memory device of claim 2, wherein one of the plurality of first string channel pillars has a center that is offset from a center of a corresponding one of the plurality of first vertical pillars that overlaps the one of the plurality of first string channel pillars in the plan view, and wherein one of the plurality of second string channel pillars has a center that is offset from a center of a corresponding one of the plurality of second vertical pillars that overlaps the one of the plurality of second string channel pillars in the plan view. ### Claim 5 (depends on 2) The semiconductor memory device of claim 2, wherein a distance between a center of the one of the plurality of first vertical pillars and a center of the one of the plurality of second vertical pillars is less than a distance between a center of one of the plurality of first string channel pillars and a center of one of the plurality of second string channel pillars that is closest to the one of the plurality of first string channel pillars. ### Claim 6 (depends on 2) The semiconductor memory device of claim 2, wherein a shortest distance between centers of first and second ones of the plurality of first string channel pillars that are adjacent each other is less than a distance between a center of one of the plurality of first string channel pillars and a center of one of the plurality of second string channel pillars that is closest to the one of the plurality of first string channel pillars. ### Claim 7 (depends on 1) The semiconductor memory device of claim 1, wherein each of the plurality of first channel pillars and the plurality of second string channel pillars comprises: a string vertical channel section that extends through one of the first and second string select lines; and a conductive pattern on an upper portion of the string vertical channel section, wherein the string vertical channel section includes polysilicon and the conductive pattern includes metal silicide. ### Claim 8 (depends on 1) The semiconductor memory device of claim 1, wherein the one of the plurality of first vertical pillars comprises a first one of the plurality of first vertical pillars, and the one of the plurality of second vertical pillars comprises a first one of the plurality of second vertical pillars, and wherein the semiconductor memory device further comprises a bit line that extends in the first direction, and the bit line is electrically connected to a second one of the plurality of first vertical pillars and a second one of the plurality of second vertical pillars. ### Claim 9 (depends on 1) The semiconductor memory device of claim 1, wherein, in the plan view, each of the first and second string select lines comprises protrusions and recesses that alternately arranged in a second direction that traverses the first direction. ### Claim 10 (depends on 1) The semiconductor memory device of claim 1, wherein each of the first and second string select lines has a straight line shape extending in a second direction that traverses the first direction. ### Claim 11 (depends on 1) The semiconductor memory device of claim 1, wherein each of the first and second string select lines comprises: first patterns spaced apart from each other in the first direction; and a second pattern between the first patterns, wherein the first patterns include metal silicide and the second pattern includes polysilicon. ### Claim 12 A semiconductor memory device comprising: a stack structure including a plurality of word lines stacked on a substrate; a plurality of first vertical pillars and a plurality of second vertical pillars that extend through the stack structure; a first string select line overlapping the plurality of first vertical pillars in a plan view; and a second string select line overlapping the plurality of second vertical pillars in the plan view and being horizontally spaced apart from the first string select line, wherein, in the plan view, at least one of the plurality of first vertical pillars and the plurality of second vertical pillars is overlapped by an area between the first and second string select lines. ### Claim 13 (depends on 12) The semiconductor memory device of claim 12, wherein, in the plan view, a shortest distance between a side of the first string select line and a side of the second string select line is less than a shortest distance between a center of one of the plurality of first vertical pillars and a center of one of the plurality of second vertical pillars. ### Claim 14 (depends on 12) The semiconductor memory device of claim 12, further comprising: a plurality of first string channel pillars that extend through the first string select line and are electrically connected to the plurality of first vertical pillars, respectively; and a plurality of second string channel pillars that extend through the second string select line and are electrically connected to the plurality of second vertical pillars, respectively, wherein a diameter of the plurality of first vertical pillars is greater than a diameter of the plurality of first string channel pillars, and wherein a diameter of the plurality of second vertical pillars is greater than a diameter of the plurality of second string channel pillars. ### Claim 15 (depends on 12) The semiconductor memory device of claim 12, wherein the plurality of word lines include a metallic material and the first and second string select lines include polysilicon. ### Claim 16 An integrated circuit device comprising: a stack structure including a plurality of word lines stacked on a substrate; a first vertical pillar extending through the stack structure; a first string select line overlapping the first vertical pillar in a plan view and extending longitudinally in a first direction, the first string select line comprising a first sidewall and a second sidewall opposite the first sidewall, and the first vertical pillar being closer to the first sidewall of the first string select line than the second sidewall of the first string select line; and a first string channel pillar extending through the first string select line and being electrically connected to the first vertical pillar, wherein a center of the first string channel pillar is offset from a center of the first vertical pillar in a second direction traversing the first direction away from the first sidewall of the first string select line in the plan view. ### Claim 17 (depends on 16) The device of claim 16, wherein a width of the first string channel pillar in the second direction is less than a width of the first vertical pillar in the second direction. ### Claim 18 (depends on 16) The device of claim 16, wherein the first vertical pillar comprises a portion not overlapped by the first string select line in the plan view. ### Claim 19 (depends on 16) The device of claim 16, further comprising: a second vertical pillar extending through the stack structure; a second string select line overlapping the second vertical pillar in the plan view and extending longitudinally in the first direction, the second string select line comprising a first sidewall and a second sidewall opposite the first sidewall, and the second vertical pillar being closer to the first sidewall of the second string select line than the second sidewall of the second string select line; and a second string channel pillar extending through the second string select line and being electrically connected to the second vertical pillar, wherein a center of the second string channel pillar is offset from a center of the second vertical pillar in the second direction away from the first sidewall of the second string select line in the plan view, and wherein the second string select line is spaced apart from the first string select line in the second direction. ### Claim 20 (depends on 19) The device of claim 19, wherein a shortest distance between one of the first and second sidewalls of the first string select line and one of the first and second sidewalls of the second string select line is greater than a shortest distance between a side of the first vertical pillar and a side of the second vertical pillar.