# US 2017/0287909 A1 · Layout method and semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0287909 A1 - Document ID: US20170287909A1 - Status: Published application - Kind: A1 - Application number: 15/372,840 - Filed: 2016-12-08 - Published: 2017-10-05 - Earliest claimed: 2016-04-05 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: In Wook OH; Jae Seok YANG; Jong Hyun LEE; Hyun Jae LEE; Sung Wook HWANG - Web page: https://patentgrep.com/patent/US20170287909A1 ## CPC - H10D 84/834: {comprising FinFETs} - G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) - G06F 30/392: Floor-planning or layout, e.g. partitioning or placement - H10D 84/8311: {the IGFETs characterised by having different channel structures} - H10D 84/8312: {the IGFETs characterised by having different source or drain region structures, e.g. IGFETs having symmetrical source or drain regions integrated with IGFETs having asymmetrical source or drain regions} - H10D 89/10: Integrated device layouts - H10W 20/43: Layouts of interconnections - H10D 84/83138: {the IGFETs characterised by having different shapes or dimensions of their gate conductors} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device includes circuit active fin lines and circuit gate lines intersecting each other in a circuit active region, dummy active fin lines and dummy gate lines intersecting each other in a dummy active region, the active fin lines and the dummy active fin lines having same width and pitch, and the circuit gate lines and the dummy gate lines having same width and pitch, wherein at least some of the dummy active fin lines are aligned with and collinear with respective circuit active fin lines, and at least some of the dummy gate lines are aligned with and collinear with respective circuit gate lines. ## Claims ### Claim at position 1 -15. (canceled) ### Claim 16 A semiconductor device, comprising: a circuit region and a dummy region, the dummy region including a first dummy region and a second dummy region, and the circuit region including a first circuit region opposing the first dummy region and a second circuit region spaced apart from the first dummy region, circuit active fin patterns in the circuit region; dummy active fin patterns in the dummy region at a same pitch as a pitch of the circuit active fin patterns; circuit gate lines in the circuit region; and dummy gate lines in the dummy region at a same pitch as a pitch of the circuit gate lines, wherein a density of the dummy active fin patterns in the first dummy region is different from a density of the circuit active fin patterns in the first circuit region, and wherein a density of the dummy active fin patterns in the second dummy region is different from a density of the dummy active fin patterns in the first dummy region. ### Claim 17 (depends on 16) The semiconductor device as claimed in claim 16, wherein one of the density of the circuit active fin patterns in the first circuit region and the density of the dummy active fin patterns in the first dummy region is higher than an average density of the circuit active fin patterns in the first and second circuit regions, and the other is lower than the average density of the circuit active fin patterns in the first and second circuit regions. ### Claim 18 (depends on 17) The semiconductor device as claimed in claim 17, wherein: the density of the circuit active fin patterns in the first circuit region is higher than the average density of the circuit active fin patterns in the first and second circuit regions, and the density of the dummy active fin patterns in the first dummy region is lower than the average density of the circuit active fin patterns in the first and second circuit regions. ### Claim 19 (depends on 17) The semiconductor device as claimed in claim 17, wherein: the density of the circuit active fin patterns in the first circuit region is lower than the average density of the circuit active fin patterns in the first and second circuit regions, and the density of the dummy active fin patterns in the first dummy region is higher than the average density of the circuit active fin patterns in the first and second circuit regions. ### Claim 20 (depends on 16) The semiconductor device as claimed in claim 16, wherein the dummy active fin patterns in the second dummy region are at a density corresponding to an average density of the circuit active fin patterns in the first and second circuit regions. ### Claim 21 (depends on 16) The semiconductor device as claimed in claim 16, wherein: the first circuit region includes a plurality of circuit portions, the plurality of circuit portions of the first circuit region includes a high-density circuit region and a low-density circuit region, the first dummy region includes a plurality of dummy portions corresponding to the plurality of circuit portions of the first circuit region, and the plurality of dummy portions of the first dummy region includes a low-density dummy region opposing the high-density circuit region and a high-density dummy region opposing the low-density circuit region. ### Claim 22 (depends on 21) The semiconductor device as claimed in claim 21, wherein: the high-density circuit region is a region in which a density of disposition of the circuit active fin patterns is higher than the low-density circuit region, and the high-density dummy region is a region in which a density of disposition of the dummy active fin patterns is higher than the low-density dummy region. ### Claim 23 (depends on 21) The semiconductor device as claimed in claim 21, wherein the number of the circuit active fin patterns in the high-density circuit region is higher than the number of the circuit active fin patterns in the low-density circuit region. ### Claim 24 (depends on 16) The semiconductor device as claimed in claim 16, wherein: the circuit active fin patterns and the dummy active fin patterns are arranged on virtual linear lines extended in a first direction, and the circuit gate lines and the dummy gate lines are arranged on virtual linear lines extended in a second direction perpendicular to the first direction. ### Claim 25 (depends on 16) The semiconductor device as claimed in claim 16, wherein, in the dummy region, a density of the dummy gate lines is higher than a density of the dummy active fin patterns. ### Claim 26 A semiconductor device, comprising: a circuit region and a dummy region adjacent to each other; circuit active fin patterns in the circuit region and having a linear shape extended in a first direction; dummy active fin patterns in the dummy region and having a linear shape extended in the first direction, the dummy active fin patterns including first-side fin patterns having end portions opposing end portions of the circuit active fin patterns; circuit gate lines in the circuit region and intersecting the circuit active fin patterns; and dummy gate lines in the dummy region and having end portions opposing end portions of the circuit gate lines, wherein sides of the circuit active fin patterns and sides of the first-side fin patterns are aligned with each other, and wherein sides of the circuit gate lines and sides of the dummy gate lines are aligned with each other. ### Claim 27 (depends on 26) The semiconductor device as claimed in claim 26, wherein: the dummy region includes a first dummy region and a second dummy region located in the second direction of the circuit region, the circuit region includes a first circuit region opposing the first dummy region and a second circuit region spaced apart from the first dummy region, the first dummy region is between the second dummy region and the first circuit region, and the dummy active fin patterns includes second-side fin patterns disposed in the first and second dummy regions. ### Claim 28 (depends on 27) The semiconductor device as claimed in claim 27, further comprising: a circuit active region within the first circuit region; a first dummy active region in the first dummy region; and a second dummy active region in the second dummy region, wherein the circuit active fin patterns are on the circuit active region, and wherein the second-side fin patterns of the dummy active fin patterns are on the first and second dummy active regions. ### Claim 29 (depends on 28) The semiconductor device as claimed in claim 28, wherein the circuit active region has a width different from a width of the first dummy active region, and the second dummy active region has a width different from a width of the first dummy active region. ### Claim 30 (depends on 29) The semiconductor device as claimed in claim 29, wherein the first dummy active region includes portions having different widths, of which the number of the dummy active fin patterns disposed on a portion having a relatively great width, among the portions having different widths, is higher than the number of the dummy active fin patterns on a portion having a relatively narrow width. ### Claim 31 A semiconductor device, comprising: circuit active fin lines and circuit gate lines intersecting each other in an active region; dummy active fin lines and dummy gate lines intersecting each other in a dummy region, the active fin lines and the dummy active fin lines having same width and pitch, and the circuit gate lines and the dummy gate lines having same width and pitch, wherein at least some of the dummy active fin lines are in contact with and collinear with respective active fin lines, and at least some of the dummy gate lines are in contact with and collinear with respective circuit gate lines. ### Claim 32 (depends on 31) The semiconductor device as claimed in claim 31, wherein the dummy active fin lines and the active fin lines connected to each other are continuous with each other to define uniform respective lines, and the dummy gate lines and the circuit gate lines connected to each other are continuous with each other to define uniform respective lines. ### Claim 33 (depends on 32) The semiconductor device as claimed in claim 32, wherein: the dummy region extends along at least two sides of the active region, and the dummy active fin lines and the active fin lines connected to each other are continuous and uniform along a boundary between the dummy region and a first side of the active region, and the dummy gate lines and the circuit gate lines are continuous and uniform along a boundary between the dummy region and a second side the active region. ### Claim 34 (depends on 31) The semiconductor device as claimed in claim 31, further comprising a first space between some of the circuit active fin lines and dummy active fin lines, and a second space between some of the circuit gate lines and the dummy gate lines. ### Claim 35 (depends on 31) The semiconductor device as claimed in claim 31, wherein a density of the dummy active fin lines in the dummy region is different from a density of the circuit active fin lines in the active region.