# US 2017/0287908 A9 · Method for forming deep trench isolation for rf devices on soi

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- Number: US 2017/0287908 A9
- Document ID: US20170287908A9
- Status: Published application
- Kind: A9
- Application number: 15/145,776
- Filed: 2016-05-03
- Published: 2017-10-05
- Earliest claimed: 2013-12-27
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation
- Inventors: HERB HE HUANG; HAITING LI; XINGCHENG JIN; XINXUE WANG; HONGBO ZHAO; FUCHENG CHEN; YANGHUI XIANG
- Web page: https://patentgrep.com/patent/US20170287908A9

## CPC

- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D 62/834: further characterised by the dopants
- H10D 64/668: {the layer being a silicide, e.g. TiSi2}
- H10D 86/01: Manufacture or treatment
- H10P 90/1906: {Preparing SOI wafers}
- H10W 10/014: {using trench refilling with dielectric materials, e.g. shallow trench isolations}
- H10W 10/061: {using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations}
- H10W 10/17: formed using trench refilling with dielectric materials, e.g. shallow trench isolations
- H10W 10/181: {Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers}
- H10D 1/20: Inductors
- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)}
- H10W 44/20: at high-frequency [HF] or radio frequency [RF]
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a silicon-on-insulator (SOI) substrate having a stack of a first semiconductor substrate, a buried insulating layer and a second semiconductor substrate formed in a first region and a deep trench isolation disposed in a second region. The method of forming the semiconductor device includes providing a SOI substrate having shallow trench isolations (STIs) and transistors formed within and on the second semiconductor substrate, respectively. The method also includes forming a hard mask over the first region and removing the STIs, the transistors, the second semiconductor substrate and the buried insulating layer in the second region using the hard mask as a mask, and forming a capping layer covering the deep trench isolation and the second semiconductor substrate including the transistors.

## Claims

### Claim 1

A semiconductor device comprising:
a silicon-on-insulator (SOI) substrate having a first region and a second region, the SOI substrate including a vertical stack of a first semiconductor substrate, a buried insulating layer, and a second semiconductor substrate arranged from bottom to top in the first region, respectively;
a plurality of transistors on the second semiconductor substrate;
a deep trench isolation exposing a surface of the first semiconductor substrate in the second region; and
a dielectric capping layer over a bottom and sidewalls of the deep trench isolation and the second semiconductor substrate.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the dielectric capping layer comprises silicon nitride.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein each of the transistors comprises a gate electrode, source/drain regions disposed on opposite of the gate electrode, and a metal silicide formed on a surface of the gate electrode and the source/drain regions.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, further comprising an ion implanted layer disposed at a bottom of the deep trench isolation.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the ion implanted layer comprises argon and boron.