# US 2017/0287906 A1 · 3d cross-point memory manufacturing process having limited lithography steps > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0287906 A1 - Document ID: US20170287906A1 - Status: Published application - Kind: A1 - Application number: 15/628,317 - Filed: 2017-06-20 - Published: 2017-10-05 - Earliest claimed: 2016-03-24 - Assignees: Western Digital Technologies, Inc. - Applicants: Western Digital Technologies, Inc. - Inventors: Mac D. APODACA; Daniel Robert SHEPARD - Web page: https://patentgrep.com/patent/US20170287906A1 ## CPC - H10D 88/00: Three-dimensional [3D] integrated devices - H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays} - H10D 1/00: Resistors, capacitors or inductors - H10D 62/115: {Dielectric isolations, e.g. air gaps} - H10W 20/42: Vias, e.g. via plugs - H10W 20/43: Layouts of interconnections - H10W 20/4441: {the principal metal being a refractory metal} - H10W 20/4446: {Refractory-metal alloys} - H10D 62/117: {Shapes of semiconductor bodies} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10B: ELECTRONIC MEMORY DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract The present disclosure generally relates to semiconductor manufactured memory devices and methods of manufacture thereof. More specifically, methods for forming a plurality of layers of a 3D cross-point memory array without the need for lithographic patterning at each layer are disclosed. The method includes depositing a patterned hard mask with a plurality of first trenches over a plurality of layers. Each of the plurality of first trenches is etched all the way through the plurality of layers. Then the hard mask is patterned with a plurality of second trenches, which runs orthogonal to the plurality of first trenches. Selective undercut etching is then used to remove each of the plurality of layers except the orthogonal metal layers from the plurality of second trenches, resulting in a 3D cross-point array with memory material only at the intersections of the orthogonal metal layers. ## Claims ### Claim 1 A memory device, comprising: a plurality of layers, wherein the plurality of layers comprises: a first metal layer comprising a first metal material; a selector layer; a memory element layer; and a second metal layer having a first portion and a second portion, wherein the second portion comprises a second metal material; a plurality of first trenches, wherein the plurality of first trenches extends through the plurality of layers, wherein each of the plurality of first trenches is filled with a first dielectric material, and wherein the second portion is disposed in each of the plurality of first trenches; and a plurality of second trenches, wherein the plurality of second trenches extends through the selector layer, the memory element layer, and the second metal layer, and wherein the plurality of second trenches runs orthogonal the plurality of first trenches. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the first metal material comprises Tungsten. ### Claim 3 (depends on 2) The memory device of claim 2, wherein the selector layer comprises an ovonic threshold switch material. ### Claim 4 (depends on 3) The memory device of claim 3, wherein the first portion and the second portion each comprise the second metal material. ### Claim 5 (depends on 4) The memory device of claim 4, wherein the second metal material comprises Titanium Nitride. ### Claim 6 (depends on 1) The memory device of claim 1, wherein the selector layer comprises an ovonic threshold switch material. ### Claim 7 (depends on 1) The memory device of claim 1, wherein the first portion and the second portion each comprise the second metal material. ### Claim 8 (depends on 1) The memory device of claim 1, wherein the second metal material comprises Titanium Nitride. ### Claim 9 (depends on 1) The memory device of claim 1, wherein a first wall and a second wall of each of the plurality of first trenches are linear and parallel, and wherein a width of each of the plurality of first trenches is consistent throughout a length of each of the plurality of first trenches. ### Claim 10 (depends on 9) The memory device of claim 9, wherein a first wall and a second wall of each of the plurality of second trenches are non-linear, and wherein each of the plurality of second trenches has a first convex portion connected to a second convex portion by a rectangular portion. ### Claim 11 A memory device, comprising: a plurality of layers, wherein the plurality of layers comprises: a first metal layer comprising a first metal material; a selector layer; a memory element layer; and a second metal layer having a first portion and a second portion, wherein the second portion comprises a second metal material, wherein the second portion has rounded edges and a top surface that is coplanar with a top surface of the first portion and a bottom surface that is coplanar with a bottom surface of the first portion; a plurality of first trenches; and a plurality of second trenches, wherein the plurality of second trenches runs orthogonal the plurality of first trenches. ### Claim 12 (depends on 11) The memory device of claim 11, wherein the first metal material comprises Tungsten. ### Claim 13 (depends on 12) The memory device of claim 12, wherein the selector layer comprises an ovonic threshold switch material. ### Claim 14 (depends on 13) The memory device of claim 13, wherein the first portion and the second portion each comprise the second metal material. ### Claim 15 (depends on 14) The memory device of claim 14, wherein the second metal material comprises Titanium Nitride. ### Claim 16 (depends on 11) The memory device of claim 11, wherein the selector layer comprises an ovonic threshold switch material. ### Claim 17 (depends on 11) The memory device of claim 11, wherein the first portion and the second portion each comprise the second metal material. ### Claim 18 (depends on 11) The memory device of claim 11, wherein the second metal material comprises Titanium Nitride. ### Claim 19 (depends on 11) The memory device of claim 11, wherein a first wall and a second wall of each of the plurality of first trenches are linear and parallel, and wherein a width of each of the plurality of first trenches is consistent throughout a length of each of the plurality of first trenches. ### Claim 20 (depends on 19) The memory device of claim 19, wherein a first wall and a second wall of each of the plurality of second trenches are non-linear, and wherein each of the plurality of second trenches has a first convex portion connected to a second convex portion by a rectangular portion.