# US 2017/0287904 A1 · Co-fabrication of vertical diodes and fin field effect transistors on the same substrate

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- Number: US 2017/0287904 A1
- Document ID: US20170287904A1
- Status: Published application
- Kind: A1
- Application number: 15/627,875
- Filed: 2017-06-20
- Published: 2017-10-05
- Earliest claimed: 2016-03-31
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Karthik Balakrishnan; Kangguo Cheng; Pouya Hashemi; Alexander Reznicek
- Web page: https://patentgrep.com/patent/US20170287904A1

## CPC

- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 8/00: Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00)
- H10D 8/01: Manufacture or treatment
- H10D 8/045: {of PN junction diodes}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6728: {Vertical TFTs}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/117: {Shapes of semiconductor bodies}
- H10D 62/128: {Anode regions of diodes}
- H10D 62/129: {Cathode regions of diodes}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 62/307: {the doping variations being parallel to the channel lengths}
- H10D 62/405: {Orientations of crystalline planes}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of forming a vertical finFET and vertical diode device on the same substrate, including forming a channel layer stack on a heavily doped layer; forming fin trenches in the channel layer stack; oxidizing at least a portion of the channel layer stack inside the fin trenches to form a dummy layer liner; forming a vertical fin in the fin trenches with the dummy layer liner; forming diode trenches in the channel layer stack; oxidizing at least a portion of the channel layer stack inside the diode trenches to form a dummy layer liner; forming a first semiconductor segment in a lower portion of the diode trenches with the dummy layer liner; and forming a second semiconductor segment in an upper portion of the diode trenches with the first semiconductor segment, where the second semiconductor segment is formed on the first semiconductor segment to form a p-n junction.

## Claims

### Claim 1

A method of forming a vertical fin field effect transistor (finFET) and a vertical diode device on the same substrate, comprising:
forming a fin trench in a channel layer stack;
forming a vertical fin in the fin trench;
forming a diode trench in the channel layer stack;
oxidizing at least a portion of the channel layer stack inside the diode trench to form a dummy layer liner;
forming a first semiconductor segment in a lower portion of the diode trench with the dummy layer liner; and
forming a second semiconductor segment in an upper portion of the diode trench with the first semiconductor segment, wherein the first semiconductor segment and the second semiconductor segment forms a p-n junction.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
oxidizing at least a portion of the channel layer stack inside the fin trench to form a dummy layer liner;
thinning an upper portion of the vertical fin; and
forming a top source drain on the thinned portion of the vertical fin.

### Claim 3 (depends on 2)

The method of claim 2, wherein the channel layer stack includes a dummy gate layer and a bottom spacer layer, and the method further comprises:
removing the dummy gate layer and the dummy layer liner from the vertical fin formed in the fin trench to expose the sidewalls of the vertical fin;
forming a high-K dielectric layer on at least an exposed surface of the bottom spacer layer and the sidewalls of the vertical fin;
forming a work function layer on the high-K dielectric layer; and
forming a gate metal layer on the work function layer.

### Claim 4 (depends on 3)

The method of claim 3, further comprising removing at least a portion of the gate metal layer, work function layer, and high-K dielectric layer on the exposed surface of the bottom spacer layer.

### Claim 5 (depends on 3)

The method of claim 3, further comprising forming a metal fill on the bottom spacer layer, where the metal fill is in contact with the gate metal layer.

### Claim 6 (depends on 1)

The method of claim 1, wherein the vertical fin is formed by epitaxial growth from a heavily doped layer below the channel layer stack, and the first semiconductor segment is formed by epitaxial growth from the heavily doped layer.

### Claim 7 (depends on 6)

The method of claim 6, wherein the top surface of the one or more vertical fins have a <100> crystal orientation.

### Claim 8 (depends on 1)

The method of claim 1, wherein the second semiconductor segment is epitaxially grown on the first semiconductor segment, and has a top surface with a <100> crystal orientation.

### Claim 9

A method of forming a vertical fin field effect transistor (finFET) and a vertical diode device on the same substrate, comprising:
forming a bottom spacer layer on a substrate;
forming a dummy gate layer on the bottom spacer layer;
forming a top spacer layer on the dummy gate layer;
forming one or more fin trenches, where at least one of the one or more fin trenches passes through the top spacer layer, the dummy gate layer, and the bottom spacer layer;
forming a vertical fin in at least one of the one or more fin trenches;
forming one or more diode trenches, where at least one of the one or more diode trenches passes through the top spacer layer, the dummy gate layer, and the bottom spacer layer;
forming a first semiconductor segment in a lower portion of at least one of the one or more diode trenches with the dummy layer liner; and
forming a second semiconductor segment in an upper portion of the at least one of the one or more diode trenches with the first semiconductor segment, where the second semiconductor segment is formed on the first semiconductor segment to form a p-n junction.

### Claim 10 (depends on 9)

The method of claim 9, further comprising forming a top source/drain on a top of the one or more vertical fins.

### Claim 11 (depends on 9)

The method of claim 9, further comprising forming a shallow trench isolation region between the one of the one or more fin trenches and one of the one or more diode trenches adjacent to the one of the one or more fin trenches.

### Claim 12 (depends on 9)

The method of claim 9, further comprising oxidizing at least a portion of the exposed portion of the dummy gate layer inside the one or more fin trenches to form a dummy layer liner, wherein the dummy layer liner provides protection to the one or more vertical fins during epitaxial growth.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
removing the dummy gate layer and the dummy layer liner from at least one of the vertical fins formed in the at least one of the one or more fin trenches with the dummy layer liner to expose the sidewalls of the at least one vertical fin;
forming a conformal high-K dielectric layer on at least an exposed surface of the sidewalls of the at least one vertical fin;
forming a conformal work function layer on the high-K dielectric layer; and
forming a conformal gate metal layer on the work function layer.

### Claim 14 (depends on 13)

The method of claim 13, where the conformal high-K dielectric layer, conformal work function layer, and/or conformal gate metal layer is formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), or a combination thereof.

### Claim 15

A method of forming a vertical fin field effect transistor (finFET) and a vertical diode device on the same substrate, comprising:
forming a vertical fin on a heavily doped layer;
forming a bottom spacer layer adjacent to the sidewall of the vertical fin;
forming a high-K dielectric layer on at least a portion of the sidewalls of the vertical fin;
forming a work function layer on the high-K dielectric layer on the portion of the sidewall of the vertical fin;
forming a gate metal layer on at least a portion of the work function layer;
forming a first semiconductor segment on the heavily doped layer; and
forming a second semiconductor segment on the first semiconductor segment, wherein the interface between the second semiconductor segment and the first semiconductor segment is a p-n junction.

### Claim 16 (depends on 15)

The method of claim 15, further comprising forming a top source/drain on the top of the vertical fin, and forming a metal fill on the bottom spacer layer, where the metal fill is in contact with the gate metal layer.

### Claim 17 (depends on 15)

The method of claim 15, wherein the top surface of the vertical fin has a <100> crystal orientation.

### Claim 18 (depends on 15)

The method of claim 15, wherein the vertical fin has a width in the range of about 6 nm to about 20 nm.

### Claim 19 (depends on 15)

The method of claim 15, wherein the high-K dielectric layer has a thickness in the range of about 1.5 nm to about 2.5 nm.

### Claim 20 (depends on 15)

The method of claim 15, further comprising forming a shallow trench isolation region between the vertical fin and the second semiconductor segment on the first semiconductor segment.