# US 2017/0287903 A1 · Variable snubber for mosfet application > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0287903 A1 - Document ID: US20170287903A1 - Status: Published application - Kind: A1 - Application number: 15/623,210 - Filed: 2017-06-14 - Published: 2017-10-05 - Earliest claimed: 2013-03-11 - Assignees: Alpha and Omega Semiconductor Incorporated - Applicants: Alpha and Omega Semiconductor Incorporated - Inventors: Sik Lui; Ji Pan - Web page: https://patentgrep.com/patent/US20170287903A1 ## CPC - H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors} - H02M 1/34: Snubber circuits - H10D 1/047: {of conductor-insulator-semiconductor capacitors, e.g. trench capacitors} - H10D 1/43: Resistors having PN junctions - H10D 1/47: Resistors having no potential barriers - H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)} - H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors} - H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates} - H10D 84/141: {VDMOS having built-in components} - H10D 84/817: {Combinations of field-effect devices and resistors only} - H02M 1/348: {Passive dissipative snubbers} - H10D 1/66: Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors - H10D 30/665: {having edge termination structures} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H02M: APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF (transformers H01F; dynamo-electric converters H02K47/00; controlling transformers, reactors or choke coils, control or regulation of electric motors, generators or dynamo-electric converters H02P) ## Abstract Aspects of the present disclosure describe MOSFET devices that have snubber circuits. The snubber circuits comprise one or more resistors with a dynamically controllable resistance that is controlled by changes to a gate and/or drain potentials of the one or more MOSFET structures during switching events. ## Claims ### Claim 1 A transistor device, comprising: one or more gated structures formed in a semiconductor substrate, wherein the one or more gated structures comprise one or more field effect transistor structures each having a gate electrode; a snubber circuit connected in parallel with the one or more gated structures, wherein the snubber circuit includes one or more three-terminal resistors with a dynamically controllable resistance controlled by changes to a gate potential of the one or more gated structures during a switching event. ### Claim 2 (depends on 1) The device of claim 1, wherein the one or more three-terminal resistors with the dynamically controllable resistance are formed above the gate electrode of one or more of the field effect transistor structures. ### Claim 3 (depends on 2) The device of claim 2, wherein the one or more three-terminal resistors each include a source terminal, a drain terminal, and a gate terminal, wherein the gate terminal is the gate electrode of one or more of the field effect transistor structures. ### Claim 4 (depends on 1) The device of claim 1, wherein the one or more three-terminal resistors with a dynamically controllable resistance are thin film transistors. ### Claim 5 (depends on 1) The device of claim 1, wherein the one or more three-terminal resistors with a dynamically controllable resistance are metal-oxide-semiconductor field effect transistors (MOSFETs). ### Claim 6 A transistor device, comprising: one or more gated structures formed in a semiconductor substrate, wherein the one or more gated structures comprise one or more field effect transistor structures each having a gate electrode; one or more three-terminal resistors with a dynamically controllable resistance controlled by changes to a gate potential of the one or more gated structures during a switching event, wherein the one or more three-terminal resistors with a dynamically controllable resistance includes polysilicon disposed above the gate electrode of one or more of the field effect transistor structures. ### Claim 7 (depends on 6) The device of claim 6, wherein the polysilicon disposed above the gate electrode is separated from the gate electrode by a dielectric layer. ### Claim 8 (depends on 7) The device of claim 7, wherein each of the one or more gated structure comprises a trenche with the gate electrode formed therewithin. ### Claim 9 (depends on 8) The device of claim 8, wherein each of the one or more gated structures further comprises a shield electrode inside the trench below the gate electrode. ### Claim 10 (depends on 6) The device of claim 6, wherein the polysilicon disposed above the gate electrode comprises a source terminal and a drain terminal more heavily doped than a body region between the source terminal and the drain terminal. ### Claim 11 A transistor device, comprising: one or more gated structures formed in a semiconductor substrate, wherein the one or more gated structures comprise one or more field effect transistor structures each having a gate electrode; a snubber circuit connected in parallel with the one or more gated structures, wherein the snubber circuit includes one or more three-terminal resistors with a dynamically controllable resistance controlled by changes to a drain potential of the one or more field effect transistor structures during a switching event. ### Claim 12 (depends on 11) The device of claim 11, wherein the one or more three-terminal resistors with the dynamically controllable resistance are formed in a termination region of the transistor device, wherein the semiconductor substrate in the termination region is maintained at the drain potential of the one or more field effect transistor structures. ### Claim 13 (depends on 12) The device of claim 12, wherein the one or more three-terminal resistors each include a source terminal, a drain terminal, and a gate terminal, wherein the gate terminal is the semiconductor substrate in the termination region that is maintained at the drain potential of the one or more field effect transistor structures. ### Claim 14 (depends on 12) The device of claim 12, wherein the one or more three-terminal resistors with a dynamically controllable resistance are thin film transistor metal-oxide-semiconductor field effect transistors (TFT MOSFETs). ### Claim 15 A transistor device, comprising: one or more gated structures formed in a semiconductor substrate, wherein the one or more gated structures comprise one or more field effect transistor structures each having a gate electrode; one or more three-terminal resistors with a dynamically controllable resistance controlled by changes to a drain potential of the one or more field effect transistor structures during a switching event, wherein the one or more three-terminal resistors with a dynamically controllable resistance includes polysilicon disposed above the semiconductor substrate in a termination region of the transistor device, wherein the semiconductor substrate in the termination region is maintained at the drain potential of the one or more field effect transistor structures. ### Claim 16 (depends on 15) The device of claim 15, wherein the polysilicon is disposed above a body type dopant region on a top portion of the semiconductor substrate in the termination region; wherein the body type dopant region is maintained at the drain potential of the one or more field effect transistor structures. ### Claim 17 (depends on 16) The device of claim 16, wherein the polysilicon disposed above the body type dopant region is separated from the body type dopant region by a dielectric layer. ### Claim 18 (depends on 15) The device of claim 15, wherein the polysilicon disposed above the gate electrode comprises a source terminal and a drain terminal more heavily doped than a body region between the source terminal and the drain terminal. ### Claim 19 (depends on 15) The device of claim 15, wherein the one or more three-terminal resistors with a dynamically controllable resistance are metal-oxide-semiconductor field effect transistors (MOSFETs). ### Claim 20 (depends on 15) The device of claim 15, wherein the one or more three-terminal resistors with a dynamically controllable resistance are junction field effect transistors (JFETs).