# US 2017/0287902 A1 · Co-fabrication of vertical diodes and fin field effect transistors on the same substrate

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- Number: US 2017/0287902 A1
- Document ID: US20170287902A1
- Status: Published application
- Kind: A1
- Application number: 15/426,739
- Filed: 2017-02-07
- Published: 2017-10-05
- Earliest claimed: 2016-03-31
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Karthik Balakrishnan; Kangguo Cheng; Pouya Hashemi; Alexander Reznicek
- Web page: https://patentgrep.com/patent/US20170287902A1

## CPC

- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H10D 8/00: Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00)
- H10D 8/01: Manufacture or treatment
- H10D 8/045: {of PN junction diodes}
- H10D 30/025: {of vertical IGFETs (of VDMOS H10D30/0291; of vertical TFTs H10D30/0318)}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6728: {Vertical TFTs}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/117: {Shapes of semiconductor bodies}
- H10D 62/128: {Anode regions of diodes}
- H10D 62/129: {Cathode regions of diodes}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- H10D 62/307: {the doping variations being parallel to the channel lengths}
- H10D 62/405: {Orientations of crystalline planes}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method of forming a vertical finFET and vertical diode device on the same substrate, including forming a channel layer stack on a heavily doped layer; forming fin trenches in the channel layer stack; oxidizing at least a portion of the channel layer stack inside the fin trenches to form a dummy layer liner; forming a vertical fin in the fin trenches with the dummy layer liner; forming diode trenches in the channel layer stack; oxidizing at least a portion of the channel layer stack inside the diode trenches to form a dummy layer liner; forming a first semiconductor segment in a lower portion of the diode trenches with the dummy layer liner; and forming a second semiconductor segment in an upper portion of the diode trenches with the first semiconductor segment, where the second semiconductor segment is formed on the first semiconductor segment to form a p-n junction.

## Claims

### Claim 1

A vertical fin field effect transistor (finFET) and a vertical diode device on the same substrate, comprising:
a vertical fin formed on a heavily doped layer, where the heavily doped layer forms a source/drain;
a bottom spacer layer on the heavily doped layer and adjacent the sidewall of the vertical fin;
a high-K dielectric layer on at least a portion of the sidewalls of the vertical fin;
a work function layer on the high-K dielectric layer on the portion of the sidewall of the vertical fin;
a gate metal layer on at least a portion of the work function layer;
a first semiconductor segment on the heavily doped layer; and
a second semiconductor segment on the first semiconductor segment, where the interface between the second semiconductor segment and the first semiconductor segment is a p-n junction.

### Claim 2 (depends on 1)

The vertical finFET and a vertical diode device of claim 1, further comprising a top source/drain on the top of the vertical fin, and a metal fill on the bottom spacer layer, where the metal fill is in contact with the gate metal layer.

### Claim 3 (depends on 1)

The vertical finFET and a vertical diode device of claim 1, wherein the top surface of the vertical fin has a <100> crystal orientation.

### Claim 4 (depends on 1)

The vertical finFET and a vertical diode device of claim 1, wherein the one or more vertical fins have a width in the range of about 6 nm to about 20 nm.

### Claim 5 (depends on 1)

The vertical finFET and a vertical diode device of claim 1, wherein the high-K dielectric layer has a thickness in the range of about 1.5 nm to about 2.5 nm.

### Claim 6 (depends on 1)

The vertical finFET and a vertical diode device of claim 1, wherein the interface between the second semiconductor segment and the first semiconductor segment is between the top surface of the bottom spacer layer and the bottom surface of the top spacer layer.

### Claim 7 (depends on 1)

The vertical finFET and a vertical diode device of claim 1, wherein a dummy layer liner is on both the second semiconductor segment and the first semiconductor segment.

### Claim 8 (depends on 1)

The vertical finFET and a vertical diode device of claim 1, further comprising a counter-doped layer on or within the substrate, wherein the heavily doped layer is in direct contact with the counter-doped layer.

### Claim 9 (depends on 8)

The vertical finFET and a vertical diode device of claim 8, wherein the heavily doped layer has a <100> or <111> crystal orientation, and the first semiconductor segments has the same crystal orientation as the heavily doped layer.

### Claim 10

A vertical fin field effect transistor (finFET) and a vertical diode device on the same substrate, comprising:
a counter-doped layer on or within a substrate;
a heavily doped layer in direct contact with the counter-doped layer;
a vertical fin on the heavily doped layer;
a first semiconductor segment on the heavily doped layer; and
a second semiconductor segment on the first semiconductor segment, where the interface between the second semiconductor segment and the first semiconductor segment is a p-n junction.

### Claim 11 (depends on 10)

The vertical finFET and a vertical diode device of claim 10, wherein the heavily doped layer has a <100> or <111> crystal orientation, and the first semiconductor segments has the same crystal orientation as the heavily doped layer.

### Claim 12 (depends on 10)

The vertical finFET and a vertical diode device of claim 10, further comprising a top anode/cathode on the second semiconductor segment.

### Claim 13 (depends on 10)

The vertical finFET and a vertical diode device of claim 10, wherein the first semiconductor segment and the second semiconductor segment have a width in the range of about 6 nm to about 20 nm.

### Claim 14 (depends on 10)

The vertical finFET and a vertical diode device of claim 10, wherein the second semiconductor segment has the opposite doping as the heavily doped layer.

### Claim 15 (depends on 10)

The vertical finFET and a vertical diode device of claim 10, wherein the vertical fin and first semiconductor segment are on a coterminous region of a substrate.

### Claim 16

A vertical fin field effect transistor (finFET) and a vertical diode device on the same substrate, comprising:
a heavily doped layer on a substrate;
a vertical fin on the heavily doped layer;
a first semiconductor segment on the heavily doped layer, where the first semiconductor segment and vertical fin are on the same coterminous region of the substrate;
a second semiconductor segment on the first semiconductor segment, where the interface between the second semiconductor segment and the first semiconductor segment is a p-n junction; and
a dummy layer liner on both the second semiconductor segment and the first semiconductor segment.

### Claim 17 (depends on 16)

The vertical finFET and a vertical diode device of claim 16, wherein the first semiconductor segment has the same doping as the heavily doped layer, and the second semiconductor segment has the opposite doping as the heavily doped layer.

### Claim 18 (depends on 16)

The vertical finFET and a vertical diode device of claim 16, further comprising a shallow trench isolation (STI) region between neighboring regions of the heavily doped layer.

### Claim 19 (depends on 16)

The vertical finFET and a vertical diode device of claim 16, further comprising a bottom spacer layer on the heavily doped layer and a sidewall of the vertical fin, where the dummy layer liner in contact with the bottom spacer layer.

### Claim 20 (depends on 16)

The vertical finFET and a vertical diode device of claim 16, wherein the top surface of the first semiconductor segment has a <100> crystal orientation.