# US 2017/0287897 A1 · High voltage esd device for finfet technology

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- Number: US 2017/0287897 A1
- Document ID: US20170287897A1
- Status: Published application
- Kind: A1
- Application number: 15/334,130
- Filed: 2016-10-25
- Published: 2017-10-05
- Earliest claimed: 2016-03-29
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Inventors: YONG LI
- Web page: https://patentgrep.com/patent/US20170287897A1

## CPC

- H10D 89/811: {using FETs as protective elements}
- H10D 12/211: {Gated diodes}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/60: Impurity distributions or concentrations
- H10D 89/611: {using diodes as protective elements}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10D 62/116: {adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An ESD protection device includes a semiconductor substrate, first and second fins, first and second doped regions adjacent to each other and having different conductivity types. The first doped region includes a first portion of the substrate and a first region of the first fin. The second doped region includes a second portion of the substrate and a second region of the first fin. The device also includes a first gate structure on a portion of first and second regions of the first fin, a first highly doped region in the first region of the first fin and having a same conductivity type as the first doped region, and a dopant concentration higher than the first doped region, and a second highly doped region in the second fin and having a same conductivity type as the second doped region, and a dopant concentration higher than the second doped region.

## Claims

### Claim 1

An electrostatic discharge (ESD) protection device, comprising:
a substrate structure comprising:
a semiconductor substrate;
a plurality of fins on the semiconductor substrate and comprising a first fin and a second fin;
a first doped region and a second doped region laterally adjacent to each other and having different conductivity types, wherein:
the first doped region comprises a first portion of the semiconductor substrate and a first region of the first fin on the first portion of the semiconductor substrate,
the second doped region comprises a second portion of the semiconductor substrate, a second region of the first fin on the second portion of the semiconductor substrate, and the second fin on the second doped region;
a first gate structure on a portion of a first region of the first fin and on a portion of a second region of the first fin;
a first highly doped region in the first region of the first fin and having a same conductivity type as the first doped region, and a dopant concentration of the first highly doped region being higher than a dopant concentration of the first doped region; and
a second highly doped region in the second fin and having a same conductivity type as the second doped region, and a dopant concentration of the second highly doped region being higher than a dopant concentration of the second doped region.

### Claim 2 (depends on 1)

The ESD protection device of claim 1, further comprising a signal input terminal configured to receive an external signal, wherein the first highly doped region is electrically connected to a gate of the first gate structure, and the second highly doped region is electrically connected to the signal input terminal.

### Claim 3 (depends on 2)

The ESD protection device of claim 2, wherein the first doped region is doped with an N-type dopant, the second doped region is doped with a P-type dopant; and
the first highly doped region and the gate of the first gate structure are connected to a power supply voltage.

### Claim 4 (depends on 2)

The ESD protection device of claim 2, wherein the first doped region is doped with a P-type dopant, the second doped region is doped with an N-type dopant; and
the first highly doped region and the gate of the first gate structure are connected to a ground potential.

### Claim 5 (depends on 1)

The ESD protection device of claim 1, wherein the first gate structure is disposed on a portion of the first region of the first fin, and on an upper surface and a side surface of the second region of the first fin.

### Claim 6 (depends on 1)

The ESD protection device of claim 1, wherein the first gate structure is disposed on a portion of the first region of the first fin and on the second region of the first fin.

### Claim 7 (depends on 1)

The ESD protection device of claim 1, further comprising a shallow trench isolation (STI) region in the second doped region and between two adjacent fins.

### Claim 8 (depends on 7)

The ESD protection device of claim 7, wherein the first gate structure is disposed on a portion of the first region of the first fin, on an upper surface and a side surface of the second region of the first fin, and on a portion of the STI region.

### Claim 9 (depends on 7)

The ESD protection device of claim 7, further comprising:
a dummy gate structure on a distal end portion of the second fin and on the STI region to define an opening in the second highly doped region.

### Claim 10 (depends on 1)

The ESD protection device of claim 1, wherein the first gate structure comprises:
an interface layer on a portion of the first region of the first fin and on a portion of the second region of the first fin;
spacers on the first fin and adjacent to opposite sides of the interface layer;
a high-k dielectric layer on the interface layer and on inner sidewalls of the spacers; and
a gate on the high-k dielectric layer.

### Claim 11 (depends on 1)

The ESD protection device of claim 1, further comprising:
a first dummy gate structure on a distal end portion of the first region of the first fin that is not covered by the first gate structure to define an opening in the first highly doped region.

### Claim 12 (depends on 11)

The ESD protection device of claim 11, wherein the first dummy gate structure comprises:
an interface layer on a distal end portion of the first region of the first fin that is not covered by the first gate structure;
first spacers on opposite sides of the first dummy gate structure and adjacent to opposite sides of the interface layer;
a high-k dielectric layer on the interface layer and on inner sidewalls of the first spacers; and
a first dummy gate on the high-k dielectric layer.

### Claim 13 (depends on 12)

The ESD protection device of claim 12, further comprising a second dummy gate structure, wherein the second dummy gate structure comprises:
the interface layer on opposite distal ends of the second fin;
second spacers on the STI region and on the distal ends of the second fin;
the high-k dielectric layer on the interface layer and on inner sidewalls of the second spacers; and
a second dummy gate on the high-k dielectric layer.

### Claim 14 (depends on 1)

The ESD protection device of claim 1, wherein the first and second highly doped regions comprise SiGe, SiC, or Si.

### Claim 15 (depends on 1)

The ESD protection device of claim 1, wherein:
the plurality of fins further comprises a third fin,
the substrate structure further comprises a third doped region adjacent the second doped region, the second and third regions having different conductivity types;
the third doped region comprises a third portion of the semiconductor substrate and a first region of the third fin;
the second doped region further comprises a second region of the third fin, the second region of the third fin being adjacent to the first region of the third fin; and
the substrate structure further comprises a third highly doped region disposed in the first region of the third fin and having a same conductivity type of the third doped region, and a conductivity type concentration of the third highly doped region higher than a conductivity type concentration of the third doped region.

### Claim 16 (depends on 15)

The ESD protection device of claim 15, wherein the first highly doped region is electrically connected to a gate of the first gate structure, and the second highly doped region is electrically connected to the signal input terminal, and the third highly doped region is electrically connected to a gate of the second gate structure.

### Claim 17 (depends on 1)

A semiconductor device comprising at least one ESD protection device as recited in claim 1.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein the at least one ESD protection device comprises a first ESD protection device and a second ESD protection device,
wherein the first doped region of the first ESD protection device comprises an N-type dopant, the second doped region of the first ESD device comprises a P-type dopant, the first highly doped region and a gate of the first gate structure of the first ESD protection device are electrically connected to a power supply voltage;
wherein the first doped region of the second ESD protection device comprises a P-type dopant, the second doped region of the second ESD protection device comprises an N-type dopant, the first highly doped region and a gate of the first gate structure of the second ESD protection device are electrically connected to a ground potential;
wherein the second highly doped region of the first ESD protection device is electrically connected to the second highly doped region of the second ESD protection device, and the second highly doped region of the first ESD protection device and the second highly doped region of the second ESD protection device are connected to a signal input terminal configured to receive an external signal.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, further comprising an internal circuit electrically connected to the signal input terminal for receiving the external signal.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, wherein the internal circuit comprises a metal oxide semiconductor (MOS) transistor having a gate connected to the signal input terminal.