# US 2017/0287831 A1 · Localized high density substrate routing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0287831 A1 - Document ID: US20170287831A1 - Status: Published application - Kind: A1 - Application number: 15/620,555 - Filed: 2017-06-12 - Published: 2017-10-05 - Earliest claimed: 2012-09-28 - Assignees: Intel Corporation - Applicants: Intel Corporation - Inventors: Robert Starkston; Debendra Mallik; John S. Guzek; Chia-Pin Chiu; Deepak Kulkarni; Ravindranath V. Mahajan - Web page: https://patentgrep.com/patent/US20170287831A1 ## CPC - H10W 20/42: Vias, e.g. via plugs - H10W 70/611: {for connecting multiple chips together} - H10W 70/618: {the bridge chips being embedded in the package substrates, interposers or redistribution layers} - H10W 90/00: Package configurations - H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs} - H10W 70/63: Vias, e.g. via plugs - H10W 72/07252: {changes in structures or sizes} - H10W 72/073: {of die-attach connectors} - H10W 72/227: {Multiple bumps having different sizes} - H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu} - H10W 72/29: Bond pads specially adapted therefor - H10W 72/921: {Structures or relative sizes of bond pads} - H10W 72/926: {Multiple bond pads having different sizes} - H10W 72/9415: {relative to the surface, e.g. recessed, protruding} - H10W 74/012: {of encapsulations on active surfaces of flip-chip devices, e.g. forming underfills} - H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Embodiments of a system and methods for localized high density substrate routing are generally described herein. In one or more embodiments an apparatus includes a medium, first and second circuitry elements, an interconnect element, and a dielectric layer. The medium can include low density routing therein. The interconnect element can be embedded in the medium, and can include a plurality of electrically conductive members therein, the electrically conductive member can be electrically coupled to the first circuitry element and the second circuitry element. The interconnect element can include high density routing therein. The dielectric layer can be over the interconnect die, the dielectric layer including the first and second circuitry elements passing therethrough. ## Claims ### Claim 1 A method of forming an interconnect element to connect between two dies, the method comprising: forming a first layer of a medium including one of glass, ceramic, or silicon; forming first high density interconnect routing in the first layer; forming a second layer of the medium in contact with the first layer; forming second high density interconnect routing in the second layer, the second high density interconnect routing electrically connected to the first high density interconnect routing; forming a third layer of the medium, the second layer situated between the first and third layers; forming third high density interconnect routing in the third layer, wherein the interconnect element includes only three layers with high density interconnect routing; forming first and second pads at a first surface of the medium in electrical contact with the third high density interconnect routing, the first and second pads at least partially exposed at a first surface of the medium; and electrically connecting first and second dies to the first and second pads, respectively, and the first and second dies to low density interconnect routing of a substrate to which the first die is electrically coupled. ### Claim 2 (depends on 1) The method of claim 1, wherein the first, second, and third layers of the high density interconnect routing include routing that is up to about 100 times more dense than routing in the substrate. ### Claim 3 (depends on 1) The method of claim 1, wherein the first high density interconnect routing includes: a first via electrically coupled to a pad of the first pads; a second via electrically coupled to a pad of the second pads; and a trace electrically connected to the first via and to the second via. ### Claim 4 (depends on 1) The method of claim 1, wherein the first pads include an exposed footprint with an area larger than a corresponding footprint of a via to connect to a pad of the first die. ### Claim 5 (depends on 1) The method of claim 1, herein the medium includes silicon. ### Claim 6 (depends on 5) The method of claim 5, wherein the medium includes one or more layers of glass or ceramic. ### Claim 7 (depends on 1) The method of claim 1, wherein the medium includes a second surface opposite the first surface, wherein the second surface is an inactive surface with no electrical connectivity to the high density routing available through the second surface. ### Claim 8 A method of forming an apparatus comprising: forming a medium including low density interconnect routing therein; forming an interconnect element including first, second, and third layers of high density interconnect routing therein, the second layer of high density interconnect routing situated between the first and third layers of high density interconnect routing, the first, second, and third layers of high density interconnect routing including a plurality of electrically conductive members, an electrically conductive member of the plurality of electrically conductive members electrically connecting the first via to the second via; embedding the interconnect element in the medium; forming a dielectric layer over the interconnect element; forming first and second vias in the dielectric layer, the first and second vias passing through the dielectric layer; and forming solder resist over the dielectric layer, the solder resist not fully covering the first and second vias. ### Claim 9 (depends on 8) The method of claim 8, wherein the first, second, and third layers of high density interconnect routing include routing that is up to about 100 times more dense than the low density interconnect routing in the medium. ### Claim 10 (depends on 8) The method of claim 8, wherein forming the interconnect element further includes: forming a third via in the third layer of high density interconnect routing; forming a first pad at least partially exposed by a surface of the interconnect element; electrically coupling the third via to the first pad; forming a fourth via in the third layer of high density interconnect routing; forming a second pad at least partially exposed by the surface of the interconnect element; electrically coupling the fourth via to the second pad; and forming a trace, the trace electrically connecting the first via and the second via. ### Claim 11 (depends on 8) The method of claim 8, wherein the first pad includes an exposed footprint with an area larger than a corresponding footprint of the first via. ### Claim 12 (depends on 8) The method of claim 8, wherein the interconnect element includes silicon. ### Claim 13 (depends on 12) The method of claim 12, wherein the interconnect element includes one or more layers of glass or ceramic. ### Claim 14 (depends on 8) The method of claim 8, wherein the interconnect element includes a second surface opposite the first surface, wherein the second surface is an inactive surface with no electrical connectivity to the first, second, and third layers of high density interconnect routing available through the second surface. ### Claim 15 A method of forming a package comprising: forming an interconnect die including first, second, and third layers of high density interconnect routing therein, the second layer of high density interconnect routing situated between the first and third layers of high density interconnect routing, the high density interconnect routing including an electrically conductive member, the interconnect die including first and second electrically conductive pads, on or at least partially in, a top surface of the interconnect die, the electrically conductive member electrically connecting the first electrically conductive via to the second electrically conductive via through the first and second electrically conductive pads; connecting, by an adhesive material the interconnect die to a substrate, the substrate including low density interconnect routing therein; forming first and second electrically conductive vias in a dielectric layer of the substrate, the first and second electrically conductive vias electrically coupled to the first and second pads, respectively; and electrically coupling first and second dies to the first and second pads, respectively. ### Claim 16 (depends on 15) The method of claim 15, further comprising: forming a metal pad on or at least partially in a top surface of the substrate, wherein the adhesive layer connects the interconnect die to the metal pad. ### Claim 17 (depends on 15) The method of claim 15, wherein a footprint of the metal pad is greater than or equal to a footprint of the interconnect die. ### Claim 18 (depends on 15) The method of claim 15, wherein the first, second, and third layers of high density interconnect routing include routing that is up to about 100 times more dense than the low density interconnect routing in the substrate. ### Claim 19 (depends on 18) The method of claim 18, wherein the interconnect die includes a bottom surface opposite the top surface, wherein the bottom surface is an inactive surface with no electrical connectivity to the first, second, and third layers of high density interconnect routing available through the bottom surface. ### Claim 20 (depends on 17) The method of claim 17, wherein the first pad includes an exposed footprint with an area larger than a corresponding footprint of the first via.