# US 2017/0287828 A1 · Semiconductor module > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0287828 A1 - Document ID: US20170287828A1 - Status: Published application - Kind: A1 - Application number: 15/511,090 - Filed: 2015-09-02 - Published: 2017-10-05 - Earliest claimed: 2014-10-15 - Assignees: Sumitomo Electric Industries, Ltd. - Applicants: Sumitomo Electric Industries, Ltd. - Inventors: Kenichi Sawada - Web page: https://patentgrep.com/patent/US20170287828A1 ## CPC - H10W 70/658: {for devices provided for in groups H10D8/00 - H10D48/00} - H10W 44/401: {Resistive arrangements (H10W44/20, H10W42/80 take precedence)} - H10W 90/00: Package configurations - H10D 30/0291: {of vertical DMOS [VDMOS] FETs} - H10D 30/665: {having edge termination structures} - H10W 72/5475: {multiple bond wires connected to common bond pads at both ends of the wires} - H10W 72/59: Bond pads specially adapted therefor - H10W 72/926: {Multiple bond pads having different sizes} - H10W 72/932: {Plan-view shape, i.e. in top view} - H10W 72/944: {Dispositions of multiple bond pads} - H10W 90/753: {between laterally-adjacent chips} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/758: {between a chip and a stacked discrete passive device} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A semiconductor module (10A) according to one embodiment includes: vertical first and second transistor chips (12A, 12B), wherein a second main electrode pad (20) formed on a back surface of the first transistor chip is mounted on and connected to a first wiring pattern (74) on the substrate, a first control electrode pad (16) formed together with a first main electrode pad on a front surface of the first transistor chip is electrically connected to a second wiring pattern (76) on the substrate, third main electrode pad (18) formed together with a second control electrode pad on a front surface of the second transistor is mounted on and connected to the first wiring pattern, and the second control electrode pad (16) formed on a back surface of the second transistor chip is electrically connected to a third wiring pattern. ## Claims ### Claim 1 A semiconductor module comprising: a substrate on which a first wiring pattern, a second wiring pattern, and a third wiring pattern are formed on a principal surface; a vertical first transistor chip mounted on the substrate; and a vertical second transistor chip mounted on the substrate, wherein the first transistor chip has a first main electrode pad and a second main electrode pad, and a first control electrode pad to which a control voltage is supplied for controlling conduction between the first main electrode pad and the second main electrode pad, the first main electrode pad and the first control electrode pad are formed on a front surface of the first transistor chip, the second main electrode pad is formed on a back surface of the first transistor chip, the second transistor chip has a third main electrode pad and a fourth main electrode pad, and a second control electrode pad to which a control voltage is supplied for controlling conduction between the third main electrode pad and the fourth main electrode pad, the third main electrode pad and the second control electrode pad are formed on a front surface of the second transistor chip, the fourth main electrode pad is formed on a back surface of the second transistor chip, the first transistor chip is mounted on the first wiring pattern such that the back surface of the first transistor chip faces the principal surface of the substrate, thereby connecting the second main electrode pad to the first wiring pattern, the first control electrode pad is electrically connected to the second wiring pattern, the second transistor chip is mounted on the first wiring pattern such that the front surface of the second transistor chip faces the principal surface of the substrate, thereby connecting the third main electrode pad to the first wiring pattern, and the second control electrode pad of the second transistor chip is electrically connected to the third wiring pattern. ### Claim 2 (depends on 1) The semiconductor module according to claim 1, wherein the first transistor chip is multiply provided, the second transistor chip is multiply provided, each one of the first transistor chips and the second transistor chips includes a wide band gap semiconductor, the first main electrode pads of the plurality of first transistor chips are connected together via a conducting wire, and the fourth main electrode pads of the plurality of second transistor chips are connected together via a conducting wire. ### Claim 3 (depends on 2) The semiconductor module according to claim 2, wherein the first control electrode pad of each of the first transistor chips is connected to the second wiring pattern via a first resistance part, and the first resistance part has a plurality of first resistance elements each of which corresponds to each of the plurality of first transistor chips and is connected to the first control electrode pad, and a linking part linking the plurality of first resistance elements together. ### Claim 4 (depends on 3) The semiconductor module according to claim 3, wherein each of the first resistance elements and the first control electrode pad are physically connected together, and each of the first resistance elements and the second wiring pattern are physically connected together. ### Claim 5 (depends on 2) The semiconductor module according to claim 2, wherein the first control electrode pad of each of the first transistor chips is connected to the second wiring pattern via the corresponding first resistance element, each of the first resistance elements and the first control electrode pad are physically connected together, and each of the first resistance elements and the second wiring pattern are physically connected together. ### Claim 6 (depends on 3) The semiconductor module according to claim 3, wherein the plurality of first transistor chips is arranged in a predetermined direction on the first wiring pattern, and the first control electrode pad of each of the first transistor chips extends in the predetermined direction. ### Claim 7 (depends on 6) The semiconductor module according to claim 6, wherein each of the first transistor chips has: a cell portion being a region that has a vertical transistor structure including a first main electrode and a second main electrode electrically connected respectively to the first main electrode pad and the second main electrode pad, and a control electrode electrically connected to the first control electrode pad, and in which a current flows in a conduction state between the first main electrode pad and the second main electrode pad; and a circumferential portion surrounding the cell portion and electrically protecting the cell portion, and at least a part of the first control electrode pad is provided on the circumferential portion. ### Claim 8 (depends on 2) The semiconductor module according to claim 2, wherein the second control electrode pads of the plurality of second transistor chips are connected to the third wiring pattern by being mounted on the third wiring pattern. ### Claim 9 (depends on 2) The semiconductor module according to claim 2, wherein the third wiring pattern has: a plurality of chip corresponding regions that respectively corresponds to the plurality of second transistor chips and is insulated from each other; and an external connection region insulated from each of the chip corresponding regions, the second control electrode pad of each of the plurality of second transistor chips is mounted on the corresponding chip corresponding region, thereby being connected to the chip corresponding region, the plurality of chip corresponding regions is connected to the external connection region via a second resistance part, and the second resistance part has a plurality of second resistance elements respectively corresponding to the plurality of chip corresponding regions and connected to the chip corresponding regions, and a second linking part linking the plurality of second resistance elements together. ### Claim 10 (depends on 3) The semiconductor module according to claim 3, wherein the second control electrode pads of the plurality of second transistor chips are connected to the third wiring pattern by being mounted on the third wiring pattern. ### Claim 11 (depends on 4) The semiconductor module according to claim 4, wherein the second control electrode pads of the plurality of second transistor chips are connected to the third wiring pattern by being mounted on the third wiring pattern. ### Claim 12 (depends on 5) The semiconductor module according to claim 5, wherein the second control electrode pads of the plurality of second transistor chips are connected to the third wiring pattern by being mounted on the third wiring pattern. ### Claim 13 (depends on 6) The semiconductor module according to claim 6, wherein the second control electrode pads of the plurality of second transistor chips are connected to the third wiring pattern by being mounted on the third wiring pattern. ### Claim 14 (depends on 7) The semiconductor module according to claim 7, wherein the second control electrode pads of the plurality of second transistor chips are connected to the third wiring pattern by being mounted on the third wiring pattern.