# US 2017/0287818 A1 · Semiconductor device and an electronic device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0287818 A1 - Document ID: US20170287818A1 - Status: Published application - Kind: A1 - Application number: 15/621,651 - Filed: 2017-06-13 - Published: 2017-10-05 - Earliest claimed: 2013-06-14 - Assignees: Renesas Electronics Corporation - Applicants: Renesas Electronics Corporation - Inventors: Akira Muto; Nobuya Koike; Masaki Kotsuji; Yukihiro Narita - Web page: https://patentgrep.com/patent/US20170287818A1 ## CPC - H10D 12/411: {Insulated-gate bipolar transistors [IGBT]} - H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs} - H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs} - H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors} - H10D 84/144: {in antiparallel diode configurations} - H10W 70/427: {Bent parts} - H10W 70/442: {of multiple leadframes in a single chip} - H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) - H10W 70/611: {for connecting multiple chips together} - H10W 72/60: Strap connectors, e.g. thick copper clips for grounding of power devices - H10W 90/811: {Multiple chips on leadframes} - H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons - H10W 70/048: {Mechanical treatments, e.g. punching, cutting, deforming or cold welding} - H10W 70/421: {Shapes or dispositions} - H10W 70/481: {for devices being provided for in groups H10D8/00 - H10D48/00} - H10W 72/07336: {Soldering or alloying} - H10W 72/07337: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy} - H10W 72/07636: {Soldering or alloying} - H10W 72/07637: {using a polymer adhesive, e.g. an adhesive based on silicone or epoxy} - H10W 72/07653: {changes in shapes} - H10W 72/631: {Shapes of strap connectors} - H10W 72/652: {comprising metals or metalloids, e.g. silver} - H10W 72/871: {Bond wires and strap connectors} - H10W 72/926: {Multiple bond pads having different sizes} - H10W 74/00: Encapsulations, e.g. protective coatings - H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10W 90/763: {between laterally-adjacent chips} - H10W 90/766: {between a chip and a stacked lead frame, conducting package substrate or heat sink} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device and an electronic device are improved in performances by supporting a large current. An emitter terminal protrudes from a first side of a sealing body, and signal terminals protrude from a second sides of the sealing body. Namely, the side of the sealing body from which the emitter terminal protrudes and the side of the sealing body from which the signal terminals protrude are different. More particularly, the signal terminals protrude from the side of the sealing body opposite the side thereof from which the emitter terminal protrudes. Further, a second semiconductor chip including a diode formed therein is mounted over a first surface of a chip mounting portion in such a manner as to be situated between the emitter terminal and the a first semiconductor chip including an IGBT formed therein in plan view. ## Claims ### Claim at position 1 1-19. (canceled) ### Claim 20 A semiconductor device, comprising: a first semiconductor chip including a first insulated gate bipolar transistor, and having a first front surface and a first back surface opposite to the first front surface, the first front surface including an emitter electrode pad and a gate electrode pad formed thereover, the first back surface including a collector electrode formed thereover; a second semiconductor chip including a diode, and having a second front surface and a second back surface opposite to the second front surface, the second front surface including an anode electrode pad formed thereover, the second back surface including a cathode electrode formed thereover; a chip mounting portion having a first surface over which the first semiconductor chip and the second semiconductor chip are mounted, and a second surface opposite to the first surface; a first lead; a second lead; a first conductive member electrically coupled with the first lead; a second conductive member electrically coupled with the second lead; and a sealing body sealing the first semiconductor chip, the second semiconductor chip, a first portion of the first lead, a first portion of the second lead, the first conductive member and the second conductive member, the sealing body having an upper surface located on the same side as the first surface of the chip mounting portion, a lower surface opposite to the upper surface, a first side surface located between the upper surface and the lower surface in a thickness direction of the sealing body, and a second side surface located between the upper surface and the lower surface in the thickness direction of the sealing body, the second side surface being opposite to the first side surface, wherein the first semiconductor chip is mounted over the first surface of the chip mounting portion such that the first back surface of the first semiconductor chip faces the first surface the chip mounting portion and such that the first semiconductor chip is arranged between the second semiconductor chip and the second lead in plan view, wherein the second semiconductor chip is mounted over the first surface of the chip mounting portion such that the second back surface of the second semiconductor chip faces the first surface the chip mounting portion and such that the second semiconductor chip is arranged between the first semiconductor chip and the first lead in plan view, wherein the emitter electrode pad of the first semiconductor chip and the anode electrode pad of the second semiconductor chip are electrically coupled with the first lead via the first conductive member, wherein the gate electrode pad of the first semiconductor chip is electrically coupled with the second lead via the second conductive member, wherein the collector electrode of the first semiconductor chip and the cathode electrode of the second semiconductor chip are electrically coupled with each other via the chip mounting portion, wherein the first lead passes through the first side surface of the sealing body such that the first portion of the first lead is embedded within the sealing body, wherein the second lead passes through the second side surface of the sealing body such that the first portion of the second lead is embedded within the sealing body, and wherein the second surface of the chip mounting portion is exposed from the sealing body such that the second surface of the chip mounting portion is not located between the upper surface of the sealing body and the lower surface of the sealing body in cross-sectional view. ### Claim 21 (depends on 20) The semiconductor device according to claim 20, wherein the second surface of the chip mounting portion is exposed from the lower surface of the sealing body. ### Claim 22 (depends on 21) The semiconductor device according to claim 21, wherein the first semiconductor chip is mounted over the first surface of the chip mounting portion such that the gate electrode pad is closer to the plurality of second leads than the emitter electrode pad in plan view. ### Claim 23 (depends on 22) The semiconductor device according to claim 22, wherein the first semiconductor chip has additional electrode pads formed over the first front surface, wherein a plurality of third leads pass through the second side surface of the sealing body such that a portion of each of the plurality of third leads is embedded within the sealing body, wherein the additional electrode pads are electrically coupled with the plurality of third lead via a plurality of third conductive members, respectively, and wherein the first semiconductor chip is mounted over the first surface of the chip mounting portion such that the additional electrode pads are closer to the plurality of third leads than the emitter electrode pad in plan view. ### Claim 24 (depends on 23) The semiconductor device according to claim 23, wherein the gate electrode pad and the additional electrode pads of the first semiconductor chip are arranged along a side of the first semiconductor chip closest to the plurality of third leads in plan view. ### Claim 25 (depends on 24) The semiconductor device according to claim 24, wherein, in plan view, the first conductive member does not overlap any of the gate electrode pad, the additional electrode pads, the second conductive member, and the plurality of third conductive members. ### Claim 26 (depends on 24) The semiconductor device according to claim 24, wherein the first conductive member is a plate-like member including copper as a main component, and wherein each of the second conductive member and the plurality of third conductive members is a metal wire including gold, copper, or aluminum as a main component. ### Claim 27 (depends on 23) The semiconductor device according to claim 23, wherein a first one of the additional electrode pads is electrically coupled with a temperature detecting diode for detecting a temperature of the first semiconductor chip, wherein a second one of the additional electrode pads is electrically coupled with a second insulated gate bipolar transistor for detecting excess current of the first insulated gate bipolar transistor, and wherein a third one of the additional electrode pads is electrically coupled with an emitter electrode of the first insulated gate bipolar transistor. ### Claim 28 (depends on 21) The semiconductor device according to claim 21, wherein the sealing body has: a third side surface located between the upper surface and the lower surface in the thickness direction of the sealing body, and located between the first side surface and the second side surface; and a fourth side surface located between the upper surface and the lower surface in the thickness direction of the sealing body, and located between the first side surface and the second side surface, and opposite to the third side surface, and wherein the chip mounting portion passes through each of the third and fourth side surfaces of the sealing body. ### Claim 29 (depends on 21) The semiconductor device according to claim 21, wherein a planar area of the chip mounting portion is larger than a total planar area of the first semiconductor chip and the second semiconductor chip, wherein a through hole extending from the first surface to the second surface is formed in a region of the chip mounting portion that is spaced from both the first semiconductor chip and the second semiconductor chip in plan view, and wherein a portion of the sealing body is filled in the through hole. ### Claim 30 (depends on 21) The semiconductor device according to claim 21, wherein a width of the first lead is larger than a width of the second lead. ### Claim 31 (depends on 21) The semiconductor device according to claim 21, wherein the lower surface of the chip mounting portion is a surface capable of being soldered with a wiring pattern of a wiring board when the semiconductor device is mounted over the wiring board. ### Claim 32 (depends on 21) The semiconductor device according to claim 21, wherein the chip mounting portion is a single piece of conductive material. ### Claim 33 (depends on 21) The semiconductor device according to claim 21, further comprising a plating layer formed on the exposed second surface of the chip mounting portion. ### Claim 34 (depends on 21) The semiconductor device according to claim 21, wherein the second surface of the chip mounting portion is located at a same height as the lower surface of the sealing body in cross-sectional view. ### Claim 35 (depends on 34) The semiconductor device according to claim 34, wherein the first lead has a second portion exposed from the sealing body, and located at a same height as the second surface of the chip mounting portion in cross-sectional view, and wherein the second lead has a second portion exposed from the sealing body, and located at the same height as the second surface of the chip mounting portion in cross-sectional view.