# US 2017/0287784 A1 · Vertical air gap subtractive etch back end metal

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- Number: US 2017/0287784 A1
- Document ID: US20170287784A1
- Status: Published application
- Kind: A1
- Application number: 15/497,728
- Filed: 2017-04-26
- Published: 2017-10-05
- Earliest claimed: 2016-03-31
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Effendi Leobandung
- Web page: https://patentgrep.com/patent/US20170287784A1

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10P 14/6336: {in the presence of a plasma [PECVD]}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10P 14/69392: {the material containing hafnium, e.g. HfO2}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 50/286: {of organic materials}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/063: {by forming conductive members before forming protective insulating material}
- H10W 20/0633: {using subtractive patterning of the conductive members}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0693: {by forming self-aligned vias}
- H10W 20/072: {of dielectric parts comprising air gaps}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 20/46: comprising air gaps
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W 20/48: Insulating materials thereof
- H10W 20/495: {Capacitive arrangements or effects of, or between wiring layers}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

After forming source/drain contact structures within an interlevel dielectric (ILD) layer to contact source/drain regions of a field effect transistor (FET), the ILD layer is recessed to expose upper portions of the source/drain contact structures. A sacrificial layer is then formed on a remaining portion of the ILD layer to laterally surround the upper portions of the source/drain contact structures. An interconnect conductor portion is subsequently formed to contact the source/drain contact structures by subtractive patterning of a metal layer that is formed on the sacrificial layer. Next, the sacrificial layer is removed, leaving a void between the interconnect conductor portion and the remaining portion of the ILD layer. An interconnect liner layer is then formed on a top surface and sidewalls of the interconnect conductor portion and on the remaining portion of the ILD layer. The interconnect liner layer encloses an air gap surrounding the upper portions of the source/drain contact structures.

## Claims

### Claim 1

A method of forming a semiconductor structure comprising:
forming source/drain regions on opposite sides of a gate structure located over a channel region of a semiconductor material layer;
forming source/drain contact structures in an interlevel dielectric (ILD) layer overlying the semiconductor material layer, each of the source/drain contact structures contacting one of the source/drain regions;
recessing the ILD layer to expose an upper portion of each of the source/drain contact structures;
forming a sacrificial layer over a remaining portion of the ILD layer to laterally surround the upper portion of each of the source/drain contact structures;
forming an interconnect conductor portion over the sacrificial layer to contact at least one of the source/drain contact structures;
removing the sacrificial layer to re-expose the upper portion of each of the source/drain contact structures; and
forming an interconnect liner portion, the interconnect liner portion having a first portion present on top and sidewall surfaces of the interconnect conductor portion and a second portion enclosing an air gap located between the interconnect conductor portion and the remaining portion of the ILD layer.

### Claim 2 (depends on 1)

The method of claim 1, wherein the interconnect conductor portion comprising a contact via and a contact line extending beneath the contact via, the contact line directly contacting the at least one of the source/drain contact structures.

### Claim 3 (depends on 2)

The method of claim 2, wherein the forming the interconnect conductor portion comprises:
forming a metal layer over the sacrificial layer and the source/drain contact structures;
patterning the metal layer to form the contact via in an upper portion of the metal layer; and
patterning a remaining portion of the metal layer to form the contact line extending beneath the contact via, wherein the contact line vertically contacts the at least one of the source/drain contact structures.

### Claim 4 (depends on 3)

The method of claim 3, further comprising annealing the metal layer prior to the patterning the metal layer.

### Claim 5 (depends on 3)

The method of claim 3, wherein the metal layer comprises Cu, W, Al, Ag, Au, a multilayered stack thereof or an alloy thereof.

### Claim 6 (depends on 2)

The method of claim 2, further comprising forming a contact level dielectric layer over the interconnect liner portion and the remaining portion of the ILD layer, the contact level dielectric layer laterally surrounding the interconnect conductor portion and having a top surface coplanar with a topmost surface of the interconnect liner portion.

### Claim 7 (depends on 1)

The method of claim 1, wherein the forming the interconnect liner portion comprises:
forming an interconnect liner layer over a top surface of the remaining portion of the ILD layer and the top and sidewall surfaces of the interconnect conductor portion, wherein the interconnect liner layer pinches off a void formed by the removal of the sacrificial layer to provide the air gap; and
removing portions of the interconnect liner layer from the top surface of the remaining portion of the ILD layer to provide the interconnect liner portion.

### Claim 8 (depends on 7)

The method of claim 7, wherein the interconnect liner layer is formed by a non-conformal deposition process.

### Claim 9 (depends on 7)

The method of claim 7, wherein the interconnect liner layer comprise silicon nitride, silicon oxide or hafnium oxide.

### Claim 10 (depends on 1)

The method of claim 1, wherein the sacrificial layer comprises amorphous carbon.

### Claim 11 (depends on 10)

The method of claim 10, wherein the removing the sacrificial layer is performed by oxygen ashing.

### Claim 12 (depends on 1)

The method of claim 1, wherein the remaining portion of the ILD layer after the recessing the ILD layer has a top surface coplanar with a topmost surface of the gate structure.

### Claim 13 (depends on 1)

The method of claim 1, wherein the remaining portion of the ILD layer after the recessing the ILD layer has a top surface located above a topmost surface of the gate structure.

### Claim 14 (depends on 1)

The method of claim 1, wherein the forming the source/drain contact structures comprises:
forming source/drain contact openings extending through the ILD layer, each of the source/drain contact openings exposing at least a portion of one of the source/drain regions;
forming a contact liner layer over sidewalls and bottom surfaces of the source/drain contact openings and a top surface of the ILD layer;
forming a contact conductive material layer over the contact liner layer to completely fill the source/drain contact openings; and
removing portions of the contact conductive material layer and the contact liner layer from the top surface of the ILD layer.

### Claim 15 (depends on 14)

The method of claim 14, wherein the contact liner layer comprises Ti, Ta, Ni, Co, Pt, W, TiN, TaN, WN, WC, Ti/TiN or Ta/TaN.

### Claim 16 (depends on 14)

The method of claim 14, wherein the contact conductive material layer comprises W, Al or Cu.

### Claim 17 (depends on 1)

The method of claim 1, wherein the gate structure comprises a gate stack comprising a gate dielectric, a gate electrode and a gate cap, and a gate spacer located on sidewalls of the gate stack.

### Claim 18 (depends on 17)

The method of claim 17, further comprising forming the gate stack, wherein the forming the gate stack comprises:
forming a material stack comprising, from bottom to top, a gate dielectric layer, a gate electrode layer and a gate cap layer over the semiconductor material; and
patterning the material stack to provide the gate stack contacting the channel region of a semiconductor material layer.

### Claim 19 (depends on 18)

The method of claim 18, further comprising forming the gate spacer, wherein the forming the gate spacer comprises:
forming a conformal gate spacer material layer on exposed surfaces of the gate stack and the semiconductor material layer; and
removing horizontal portions of the gate spacer material layer.

### Claim 20 (depends on 1)

The method of claim 1, wherein the forming the source/drain regions is performed by ion implantation.