# US 2017/0287777 A1 · Methods of forming mis contact structures on transistor devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0287777 A1 - Document ID: US20170287777A1 - Status: Published application - Kind: A1 - Application number: 15/091,138 - Filed: 2016-04-05 - Published: 2017-10-05 - Earliest claimed: 2016-04-05 - Assignees: Globalfoundries Inc. - Applicants: GLOBALFOUNDRIES Inc. - Inventors: Suraj K. Patil; Zhiguo Sun; Keith Tabakman - Web page: https://patentgrep.com/patent/US20170287777A1 ## CPC - H10D 64/251: {Source or drain electrodes for field-effect devices} - H10D 30/021: {of FETs having insulated gates [IGFET]} - H10P 14/42: using a gas or vapour - H10W 20/033: {in openings in dielectrics} - H10W 20/051: {by ion implantation} - H10W 20/0526: {by thermal treatment thereof} - H10W 20/076: {in via holes or trenches} - H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes - H10W 20/4437: {the principal metal being a transition metal} - H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract One method disclosed herein includes performing a plurality of conformal deposition processes to form first, second and third layers of material within a contact opening, wherein the first layer comprises a contact insulating material, the second layer comprises a metal-containing material and the third layer comprises a conductive cap material, wherein the third layer is positioned above the second layer. The method further includes forming a contact ion implant region that is positioned at least partially in at least one of the first, second or third layers of material, forming a conductive material above the third layer and removing portions of the layers of material positioned outside of the contact opening. ## Claims ### Claim 1 A method of forming an MIS contact structure on a transistor, comprising: forming a contact opening in at least one layer of insulating material, said contact opening exposing an upper surface portion of a source/drain (S/D) region of said transistor; performing a plurality of conformal deposition processes to conformally deposit first, second and third layers of material within said contact opening, wherein performing said plurality of conformal deposition processes comprises: performing a first conformal deposition process to conformally deposit said first layer within said opening, wherein said first layer comprises a contact insulating material, is positioned on and in direct contact with said exposed upper surface portion of said S/D region, and covers an entirety of sidewall surfaces of said contact opening; performing a second conformal deposition process to conformally deposit said second layer within said opening, wherein said second layer comprises a metal-containing material and is positioned on said first layer; and performing a third conformal deposition process to conformally deposit said third layer within said opening, wherein said third layer comprises a conductive cap material and is positioned above said second layer; performing a contact ion implantation process to form a contact ion implant region comprising a contact ion that is positioned at least partially in at least one of said first, second or third layers of material; forming a fourth layer of material comprising a conductive material above said third layer such that said fourth layer overfills said contact opening; and performing at least one process operation to remove portions of said first, second, third and fourth layers of material positioned outside of said contact opening. ### Claim 2 (depends on 1) The method of claim 1, wherein said third layer is formed on and in contact with said second layer. ### Claim 3 (depends on 1) The method of claim 1, wherein said first layer comprises one of a high-k insulating material (k value of 10 or greater), zirconium oxide (ZrO2), hafnium oxide (HfO2), hafnium zirconium oxide (HfZrOx), HfSiOxNy, niobium oxide (NbxOy), cerium oxide (CeO2), tantalum oxide (Ta2O5), titanium tantalum oxide (TiTaxOy), strontium titanate (SrTiO3), aluminum oxide (Al2O3), nickel oxide (NixOy), titanium oxide (TiO2), lanthanum oxide (La2O3) or zinc oxide (ZnO). ### Claim 4 (depends on 1) The method of claim 1, wherein said second layer comprises an N-type metal-containing layer of material. ### Claim 5 (depends on 1) The method of claim 1, wherein said second layer comprises a P-type metal-containing layer. ### Claim 6 (depends on 1) The method of claim 1, wherein said third layer comprises one of titanium nitride, nickel nitride, tungsten nitride or an electrically conductive metal nitride. ### Claim 7 (depends on 1) The method of claim 1, further comprising, after performing said contact ion implantation process, performing an anneal process at a temperature that falls within a range of about 250-850° C. ### Claim 8 (depends on 7) The method of claim 7, wherein said anneal process is performed prior to forming said fourth layer. ### Claim 9 (depends on 7) The method of claim 7, wherein said anneal process is performed after forming said fourth layer. ### Claim 10 (depends on 1) The method of claim 1, wherein said fourth layer comprises one of copper, tungsten, cobalt, nickel, aluminum or doped polysilicon. ### Claim 11 (depends on 1) The method of claim 1, wherein performing said contact ion implantation process comprises performing said contact ion implantation process with a dose of said contact ion that falls within a range of about 1×1014-1×1015 ion/cm2 and at an energy level that falls within a range of about 0.1-10 keV. ### Claim 12 (depends on 1) The method of claim 1, wherein said transistor device is an N-type transistor device, said S/D region is an N-doped S/D region that is doped with an N-type dopant ion and wherein performing said contact ion implantation process comprises performing said contact ion implantation process with a contact ion that is different than said N-type dopant ion. ### Claim 13 (depends on 1) The method of claim 1, wherein said transistor device is an N-type transistor device and wherein performing said contact ion implantation process comprises performing said contact ion implantation process with a contact ion comprising one of phosphorous (P), magnesium (Mg) or antimony (Sb). ### Claim 14 (depends on 1) The method of claim 1, wherein said transistor device is a P-type transistor device, said S/D region is a P-doped S/D region that is doped with a P-type dopant ion and wherein performing said contact ion implantation process comprises performing said contact ion implantation process with a contact ion that is different than said P-type dopant ion. ### Claim 15 (depends on 1) The method of claim 1, wherein said transistor device is a P-type transistor device and wherein performing said contact ion implantation process comprises performing said contact ion implantation process with a contact ion comprising one of aluminum (Al), nickel (Ni), gallium (Ga) or nitrogen (N). ### Claim 16 (depends on 1) The method of claim 1, wherein said transistor device is an N-type transistor device, said first layer comprises zirconium oxide, said second layer comprises a P-type metal-containing layer, said third layer comprises titanium nitride and wherein performing said contact ion implantation process comprises performing said contact ion implantation process with a contact ion comprising one of phosphorous (P), magnesium (Mg) or antimony (Sb). ### Claim 17 (depends on 1) The method of claim 1, wherein said transistor device is a P-type transistor device, said first layer comprises zirconium oxide, said second layer comprises an N-type metal-containing layer of material, said third layer comprises titanium nitride and wherein performing said contact ion implantation process comprises performing said contact ion implantation process with a contact ion comprising one of aluminum (Al), nickel (Ni), gallium (Ga) or nitrogen (N). ### Claim 18 (depends on 1) The method of claim 1, wherein performing said at least one process operation comprises performing at least one chemical mechanical polishing process operation. ### Claim 19 A method of forming an MIS contact structure on a transistor, comprising: forming a contact opening in at least one layer of insulating material, said contact opening exposing an upper surface portion of a source/drain (S/D) region of said transistor that is doped with a source/drain (S/D) dopant ion; performing a plurality of conformal deposition processes to conformally deposit first, second and third layers of material within said contact opening wherein performing said plurality of conformal deposition processes comprises: performing a first conformal deposition process to conformally deposit said first layer within said opening, wherein said first layer comprises one of zirconium oxide or hafnium oxide, is positioned on and in direct contact with said exposed upper surface portion of said S/D region, and covers an entirety of sidewall surfaces of said contact opening; performing a second conformal deposition process to conformally deposit said second layer within said opening, wherein said second layer comprises a metal-containing material and is positioned on and in contact with said first layer; and performing a third conformal deposition process to conformally deposit said third layer within said opening, wherein said third layer comprises a conductive cap material and is positioned above said second layer; performing a contact ion implantation process to form a contact ion implant region comprising a contact ion that is positioned at least partially in at least one of said first, second or third layers of material, wherein said contact ion comprises an ion that is different than said S/D dopant ion; forming a fourth layer of material comprising a conductive material above said third layer such that said fourth layer overfills said contact opening; and performing at least one process operation to remove portions of said first, second, third and fourth layers of material positioned outside of said contact opening. ### Claim 20 (depends on 19) The method of claim 19, further comprising, after performing said contact ion implantation process, performing an anneal process at a temperature that falls within a range of about 250-850° C. ### Claim 21 (depends on 20) The method of claim 20, wherein said anneal process is performed prior to forming said fourth layer. ### Claim 22 (depends on 20) The method of claim 20, wherein said anneal process is performed after forming said fourth layer. ### Claim 23 (depends on 19) The method of claim 19, wherein said transistor device is an N-type transistor device and wherein performing said contact ion implantation process comprises performing said contact ion implantation process with a contact ion comprising one of phosphorous (P), magnesium (Mg) or antimony (Sb). ### Claim 24 (depends on 19) The method of claim 19, wherein said transistor device is a P-type transistor device and wherein performing said contact ion implantation process comprises performing said contact ion implantation process with a contact ion comprising one of aluminum (Al), nickel (Ni), gallium (Ga) or nitrogen (N). ### Claim 25 (depends on 19) The method of claim 19, wherein said transistor device is an N-type transistor device, said second layer comprises a P-type metal-containing layer, said third layer comprises titanium nitride and wherein performing said contact ion implantation process comprises performing said contact ion implantation process with a contact ion comprising one of phosphorous (P), magnesium (Mg) or antimony (Sb). ### Claim 26 (depends on 19) The method of claim 19, wherein said transistor device is a P-type transistor device, said second layer comprises an N-type metal-containing layer of material, said third layer comprises titanium nitride and wherein performing said contact ion implantation process comprises performing said contact ion implantation process with a contact ion comprising one of aluminum (Al), nickel (Ni), gallium (Ga) or nitrogen (N).