# US 2017/0287737 A1 · Method for manufacturing semiconductor device

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- Number: US 2017/0287737 A1
- Document ID: US20170287737A1
- Status: Published application
- Kind: A1
- Application number: 15/428,176
- Filed: 2017-02-09
- Published: 2017-10-05
- Earliest claimed: 2016-03-30
- Assignees: Renesas Electronics Corporation
- Applicants: Renesas Electronics Corporation
- Inventors: Yukinori TASHIRO
- Web page: https://patentgrep.com/patent/US20170287737A1

## CPC

- H10W 74/016: {using moulds}
- B29C 45/0046: {Details relating to the filling pattern or flow paths or flow characteristics of moulding material in the mould cavity}
- B29C 45/14655: {connected to or mounted on a carrier, e.g. lead frame}
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/424: {Cross-sectional shapes (H10W70/481 takes precedence)}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/0198: {batch processes}
- H10W 74/129: {forming a chip-scale package [CSP]}
- B29C 45/2708: {Gates (B29C45/2703 takes precedence)}
- H10W 46/503: {Located in scribe lines}
- H10W 72/073: {of die-attach connectors}
- H10W 72/075: {of bond wires}
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- B29C: SHAPING OR JOINING OF PLASTICS; SHAPING OF MATERIAL IN A PLASTIC STATE, NOT OTHERWISE PROVIDED FOR; AFTER-TREATMENT OF THE SHAPED PRODUCTS, e.g. REPAIRING (making preforms B29B11/00; making laminated products by combining previously unconnected layers which become one product whose layers will remain together B32B37/00 - B32B41/00)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

The reliability of a semiconductor device is improved. During resin injection in a molding step, in a plan view, a plurality of gates of a molding die are arranged at positions different from those over extended lines of a plurality of dicing regions and a resin is injected from the gates. In this way, it becomes possible to reduce entrainment of air in the dicing regions and to lower an occurrence rate of voids. As a consequence, it becomes possible to suppress an occurrence of poor appearance such as formation of voids in a sealing body and to suppress formation of a starting point of a crack which may occur during a reflow process. Thus, the reliability of the semiconductor device can be improved.

## Claims

### Claim 1

A method for manufacturing a semiconductor device, comprising the steps of:
(a) preparing a base material having a main surface, a first side included in the main surface, a second side opposed to the first side included in the main surface, a plurality of first regions extending from the first side toward the second side over the main surface, a plurality of second regions formed between the respective first regions over the main surface, and a plurality of third regions formed between the first side and the second regions;
(b) after step (a), mounting a semiconductor chip in each of the of second regions of the base material;
(c) after step (b), covering the first regions and the second regions with one cavity of a molding die and arranging the base material in the molding die such that a plurality of gates is arranged in the third regions; and
(d) after step (c), injecting resin into the cavity from the plurality of gates and forming a sealing resin layer over the main surface of the base material,
wherein, in a plan view, each of the plurality of first regions have a groove formed along each of the plurality of the first region, respectively,
wherein, in a plan view, over a straight line vertically crossing the first side and the second side, one of the plurality of second regions and one of the plurality of third regions are arranged in a continuously joined manner, and
wherein, during the step (d), the resin is injected from the first side toward the second side.

### Claim 2 (depends on 1)

The method for manufacturing a semiconductor device according to claim 1,
wherein, in the step (d), in a plan view, the resin is supplied into the cavity from the plurality of gates arranged over an extended line along a direction in which the second region continuously joins the third region and, at the same time, the vertex of the tip which advances toward the second side of the resin passes through a region between the semiconductor chip and the first region.

### Claim 3 (depends on 1)

The method for manufacturing a semiconductor device according to claim 1,
wherein a side of the second region is shorter than the sum of a gap between a plurality of gate patterns arranged along the first side of the base material and the second region and a gap between an air vent pattern arranged along the second side of the base material and the second region.

### Claim 4 (depends on 1)

The method for manufacturing a semiconductor device according to claim 1,
wherein the plurality of gates are arranged in one of the second regions.

### Claim 5 (depends on 1)

The method for manufacturing a semiconductor device according to claim 1,
wherein the base material is a wiring substrate having a first surface over which the semiconductor chip is mounted and a second surface opposite to the first surface, and
wherein a wiring part and an insulating film which is covering the wiring part are formed over the first surface.

### Claim 6 (depends on 5)

The method for manufacturing a semiconductor device according to claim 5,
wherein the groove in the first region is a concave stepped portion having a wall part including the wiring part and the insulating film.

### Claim 7

A method for manufacturing a semiconductor device, comprising the steps of:
(a) preparing a base material having a main surface, a first side included in the main surface, a second side opposed to the first side included in the main surface, a plurality of first regions extending from the first side toward the second side over the main surface, a plurality of second regions formed between the respective first regions over the main surface, and a plurality of third regions formed between the first side and the second regions;
(b) after step (a) mounting a semiconductor chip in each of the plurality of second regions of the base material;
(c) after step (b), covering the first regions and the second regions with one cavity of a molding die and arranging the base material in the molding die such that a plurality of gates is arranged in the third regions; and
(d) after step (c), injecting resin into the cavity from the plurality of gates and forming a sealing resin layer over the main surface of the base material,
wherein each of the plurality of first regions have groove formed along the first regions, respectively,
wherein, in a plan view, over a straight line vertically crossing the first side and the second side, one of the second regions and one of the third regions are arranged in a continuously joined manner, and
wherein, during the step (d), the resin is injected from the first side toward the second side and, in a plan view, the resin is injected such that the vertex of the tip which advances toward the second side most rapidly of the resin supplied into the cavity is located in the second region

### Claim 8 (depends on 7)

The method for manufacturing a semiconductor device according to claim 7,
wherein, in the step (d), in a plan view, the resin is supplied into the cavity from the plurality of gates arranged over an extended line along a direction in which the second region continuously joins the third region and, the vertex of the tip which advances toward the second side of the resin passes through a region between the semiconductor chip and the first region.

### Claim 9 (depends on 7)

The method for manufacturing a semiconductor device according to claim 7,
wherein a side of the second regions is shorter than the sum of a gap between a plurality of gate patterns arranged along the first side of the base material and the second regions and a gap between an air vent pattern arranged along the second side of the base material and the second region.

### Claim 10 (depends on 7)

The method for manufacturing a semiconductor device according to claim 7,
wherein the plurality of gates are arranged in one of the second regions.

### Claim 11 (depends on 7)

The method for manufacturing s semiconductor device according to claim 7,
wherein the base material is a wiring substrate having a first surface over which the semiconductor chip is mounted and a second surface opposite to the first surface, and
wherein a wiring part and an insulating film which is covering the wiring part are formed over the first surface.

### Claim 12 (depends on 11)

The method for manufacturing a semiconductor device according to claim 11,
wherein the groove in the first region is a concave stepped portion having a wall part including the wiring part and the insulating film.