# US 2017/0287733 A1 · Package-on-package assembly with wire bonds to encapsulation surface

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- Number: US 2017/0287733 A1
- Document ID: US20170287733A1
- Status: Published application
- Kind: A1
- Application number: 15/628,851
- Filed: 2017-06-21
- Published: 2017-10-05
- Earliest claimed: 2011-05-03
- Assignees: Tessera, Inc.
- Applicants: Tessera, Inc.
- Inventors: Hiroaki SATO; Teck-Gyu KANG; Belgacem HABA; Philip R. OSBORN; Wei-Shun WANG; Ellis CHAU; Ilyas MOHAMMED; Norihito MASUDA; Kazuo SAKUMA; Kiyoaki HASHIMOTO; Kurosawa INETARO; Tomoyuki KIKUCHI
- Web page: https://patentgrep.com/patent/US20170287733A1

## CPC

- H10F 39/804: {Containers or encapsulations}
- H10F 39/806: {Optical elements or arrangements associated with the image sensors}
- H10W 70/465: {Bumps or wires}
- H10W 70/68: Shapes or dispositions thereof
- H10W 74/111: {the semiconductor body being completely enclosed}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/00: Package configurations
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 72/07254: {changes in dispositions}
- H10W 72/07554: {changes in dispositions}
- H10W 72/247: {Dispositions of multiple bumps}
- H10W 72/248: {Top-view layouts, e.g. mirror arrays}
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/5363: {the connected ends being wedge-shaped}
- H10W 72/5445: {being orthogonal to a side surface of the chip, e.g. parallel arrangements}
- H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements}
- H10W 72/547: {Dispositions of multiple bond wires}
- H10W 72/552: {comprising metals or metalloids, e.g. silver}
- H10W 72/5522: {comprising gold [Au]}
- H10W 72/5524: {comprising aluminium [Al]}
- H10W 72/5525: {comprising copper [Cu]}
- H10W 72/859: {Bump connectors and bond wires}
- H10W 72/865: {Die-attach connectors and bond wires}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/951: {Materials of bond pads}
- H10W 74/00: Encapsulations, e.g. protective coatings
- H10W 74/01: Manufacture or treatment
- H10W 74/10: characterised by their shape or disposition
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/28: the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/732: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/752: {between stacked chips}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Apparatuses relating to a microelectronic package are disclosed. In one such apparatus, a substrate has first contacts on an upper surface thereof. A microelectronic die has a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die. Wire bonds have bases joined to the first contacts and have edge surfaces between the bases and corresponding end surfaces. A first portion of the wire bonds are interconnected between a first portion of the first contacts and the second contacts. The end surfaces of a second portion of the wire bonds are above the upper surface of the microelectronic die. A dielectric layer is above the upper surface of the substrate and between the wire bonds. The second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.

## Claims

### Claim 1

A microelectronic package, comprising:
a substrate having first contacts on an upper surface thereof;
a microelectronic die having a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die;
wire bonds having bases joined to the first contacts and having edge surfaces between the bases and corresponding end surfaces;
a first portion of the wire bonds interconnected between a first portion of the first contacts and the second contacts;
the end surfaces of a second portion of the wire bonds above the upper surface of the microelectronic die; and
a dielectric layer above the upper surface of the substrate and between the wire bonds;
wherein the second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.

### Claim 2 (depends on 1)

The microelectronic package according to claim 1, wherein the uppermost portions have corresponding sections of the edge surfaces flush with the upper surface of the dielectric layer.

### Claim 3 (depends on 1)

The microelectronic package according to claim 1, wherein the uppermost portions have corresponding sections of the edge surfaces above the upper surface of the dielectric layer.

### Claim 4 (depends on 1)

The microelectronic package according to claim 1, further comprising a redistribution layer above and on the upper surface of the dielectric layer and interconnected to the end surfaces of the second portion of the first wire bonds for electrical conductivity.

### Claim 5

A microelectronic package, comprising:
a substrate having first contacts on an upper surface thereof;
a microelectronic die having a lower surface facing the upper surface of the substrate and having second contacts on an upper surface of the microelectronic die;
wire bonds having bases joined to the first contacts and having edge surfaces between the bases and corresponding end surfaces, the wire bonds having bends therein between the bases and the end surfaces;
a first portion of the wire bonds interconnected between a first portion of the first contacts and the second contacts;
the end surfaces of a second portion of the wire bonds above the upper surface of the microelectronic die; and
a dielectric layer above the upper surface of the substrate and between the wire bonds.

### Claim 6 (depends on 5)

The microelectronic package according to claim 5, wherein an upper surface of the dielectric layer defines recesses around uppermost portions of the second portion of the wire bonds, the uppermost portions extending in the recesses corresponding thereto.

### Claim 7 (depends on 6)

The microelectronic package according to claim 6, wherein the recesses are defined responsive to removal of corresponding uppermost portions of coatings respectively disposed around portions of the edge surfaces.

### Claim 8 (depends on 6)

The microelectronic package according to claim 6, further comprising a redistribution layer above and on the upper surface of the dielectric layer and interconnected to the end surfaces of the second portion of the first wire bonds for electrical conductivity.

### Claim 9

A microelectronic package, comprising:
a substrate having first contacts on an upper surface thereof and second contacts on a lower surface thereof, the substrate defining a hole therein;
a microelectronic die having a lower surface facing the upper surface of the substrate and having third contacts on the lower surface of the microelectronic die, the microelectronic die positioned over the hole for alignment with the third contacts;
first wire bonds having bases joined to the first contacts and having edge surfaces between the bases and corresponding end surfaces;
second wire bonds interconnected between the second contacts and the third contacts; and
a dielectric layer above the upper surface of the substrate and between the wire bonds.

### Claim 10 (depends on 9)

The microelectronic package according to claim 9, wherein an upper surface of the dielectric layer defines recesses around uppermost portions of the second portion of the wire bonds, the uppermost portions extending in the recesses corresponding thereto.

### Claim 11 (depends on 9)

The microelectronic package according to claim 9, wherein the second portion of the wire bonds have uppermost portions thereof bent over to be parallel with an upper surface of the dielectric layer.

### Claim 12 (depends on 11)

The microelectronic package according to claim 11, wherein the uppermost portions have corresponding sections of the edge surfaces flush with the upper surface of the dielectric layer.

### Claim 13 (depends on 11)

The microelectronic package according to claim 11, wherein the uppermost portions have corresponding sections of the edge surfaces above the upper surface of the dielectric layer.

### Claim 14 (depends on 11)

The microelectronic package according to claim 11, further comprising a redistribution layer above and on the upper surface of the dielectric layer and interconnected to the end surfaces of the second portion of the first wire bonds for electrical conductivity.