# US 2017/0287709 A1 · Semiconductor Substrate with Stress Relief Regions > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0287709 A1 - Document ID: US20170287709A1 - Status: Published application - Kind: A1 - Application number: 15/090,904 - Filed: 2016-04-05 - Published: 2017-10-05 - Earliest claimed: 2016-04-05 - Assignees: Infineon Technologies Austria AG - Applicants: Infineon Technologies Austria AG - Inventors: Simone Lavanga; Uttiya Chowdhury - Web page: https://patentgrep.com/patent/US20170287709A1 ## CPC - H10P 14/3252: {Alternating layers, e.g. superlattice} - H10D 30/015: {of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT} - H10D 30/4735: {having delta-doped or planar-doped donor layers} - H10D 62/402: {Amorphous materials} - H10D 62/405: {Orientations of crystalline planes} - H10D 62/53: the imperfections being within the semiconductor body - H10D 62/8164: {comprising only semiconductor materials (potential variation in long-range structurally-disordered materials H10D62/8163)} - H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions - H10D 62/85: being Group III-V materials, e.g. GaAs - H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN} - H10P 14/27: {using selective deposition, e.g. simultaneous growth of monocrystalline and non-monocrystalline semiconductor materials} - H10P 14/2905: {Silicon, silicon germanium or germanium} - H10P 14/2926: {Crystal orientations} - H10P 14/3216: {Nitrides} - H10P 14/3254: {Graded layers} - H10P 14/3416: {Nitrides} - H10P 14/36: {characterised by treatments done before the formation of the materials} - H10D 30/475: {having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A crystalline base substrate including a first semiconductor material and having a main surface is provided. The base substrate is processed so as to damage a lattice structure of the base substrate in a first region that extends to the main surface without damaging a lattice structure of the base substrate in second regions that are adjacent to the first region. A first semiconductor layer of a second semiconductor material is formed on a portion of the main surface that includes the first and second regions. A third region of the first semiconductor layer covers the first region of the base substrate, and a fourth region of the first semiconductor layer covers the second region of the base substrate. The third region has a crystalline structure that is disorganized relative to a crystalline structure of the fourth region. The first and second semiconductor materials have different coefficients of thermal expansion. ## Claims ### Claim 1 A method of forming a compound semiconductor substrate, comprising: providing a crystalline base substrate comprising a first semiconductor material and having a main surface; processing the base substrate so as to damage a lattice structure of the base substrate in a first region that extends to the main surface without damaging a lattice structure of the base substrate in second regions that are adjacent to the first region; and forming a first semiconductor layer comprising a second semiconductor material on a portion of the main surface that includes the first and second regions, a third region of the first semiconductor layer covering the first region of the base substrate, a fourth region of the first semiconductor layer covering the second region of the base substrate, the third region having a crystalline structure that is disorganized relative to a crystalline structure of the fourth region; wherein the first semiconductor material has a different coefficient of thermal expansion than the second semiconductor material. ### Claim 2 (depends on 1) The method of claim 1, wherein providing the crystalline base substrate comprises providing a monocrystalline semiconductor base substrate with the main surface extending along a single crystal lattice plane, and wherein processing the base substrate comprises locally damaging the crystalline structure of the base substrate so as to disrupt the single crystal lattice plane in the first regions. ### Claim 3 (depends on 2) The method of claim 2, wherein the base substrate is a silicon substrate, wherein the main surface extends along a <111> crystal lattice plane of the silicon substrate, and wherein locally damaging the crystalline structure of the base substrate comprises exposing crystal lattice planes different than the <111> crystallographic plane at the main surface. ### Claim 4 (depends on 2) The method of claim 2, wherein processing the base substrate comprises: forming a patterned mask on the main surface, the patterned mask exposing the first regions of the base substrate and covering the second regions of the base substrate; and applying charged ions that damage the crystalline structure of the semiconductor base substrate to the exposed first regions while the second regions remain covered by the mask. ### Claim 5 (depends on 4) The method of claim 4, wherein applying the charged ions comprises at least one of: plasma treatment or ion implantation. ### Claim 6 (depends on 2) The method of claim 2, wherein forming the first semiconductor layer comprises epitaxially depositing the second semiconductor material on the portion of the main surface that includes the first and second regions such that the crystalline structure of the second semiconductor material is dependent upon the crystalline structure of the base substrate. ### Claim 7 (depends on 6) The method of claim 6, wherein epitaxially depositing the second semiconductor material comprises a high temperature epitaxial deposition process, wherein the base substrate and the first semiconductor layer are cooled after the high temperature deposition epitaxial process, wherein the cooling process induces a mechanical stress in the first semiconductor layer due to the different coefficients of thermal expansion, and wherein third region disrupts the mechanical stress. ### Claim 8 (depends on 7) The method of claim 7, wherein the third region cracks during the high temperature epitaxial deposition process or the cooling process, and wherein the cracks disrupt the mechanical stress by permitting the fourth region to expand or contract under the mechanical stress. ### Claim 9 (depends on 6) The method of claim 6, wherein epitaxially depositing the second semiconductor material comprises: epitaxially depositing a transition layer on the main surface, the transition layer comprising the second semiconductor material, a fifth region of the transition layer being formed on the first region of the base substrate, a sixth region of the first semiconductor being formed on the second region of the base substrate; and epitaxially depositing the first semiconductor layer on the transition layer, the first semiconductor layer comprising the second semiconductor material and not the first semiconductor material, the third region of the first semiconductor layer being formed on the fifth region of the transition layer, the fourth region of the first semiconductor layer being formed on the sixth region of the transition layer. ### Claim 10 (depends on 6) The method of claim 6, wherein the epitaxial deposition process is controlled such that the third regions are polycrystalline regions of the second semiconductor material. ### Claim 11 (depends on 6) The method of claim 6, wherein the epitaxial deposition process is controlled such that the third regions are amorphous regions of the second semiconductor material. ### Claim 12 (depends on 2) The method of claim 2, wherein the third regions form spaced apart tracks in the first semiconductor layer, the method further comprising: cutting the compound semiconductor substrate along the tracks so as to form one or more semiconductor dies, each one of the dies comprising one or more of the fourth regions of the first semiconductor layer. ### Claim 13 (depends on 2) The method of claim 2, wherein the first semiconductor material is silicon and the second semiconductor material is a type III-V semiconductor nitride. ### Claim 14 (depends on 13) The method of claim 13, wherein the third regions occupy 50% or more of an overall area of the compound semiconductor substrate, and wherein the fourth regions occupy 50% or less of an overall area of the compound semiconductor substrate. ### Claim 15 (depends on 14) The method of claim 14, further comprising: forming one or more HEMT devices in the compound substrate, wherein the fourth regions provide an active channel region for the one or more HEMT devices. ### Claim 16 A method of forming a compound semiconductor substrate, comprising: providing a crystalline base substrate comprising a first semiconductor material and having a main surface; forming a first semiconductor layer on the main surface and comprising a pair of tracks disposed on either side of active device regions, the first semiconductor layer being formed from a second semiconductor material having a different coefficient of thermal expansion than the first semiconductor material, the pair of tracks having a relatively weaker crystalline structure than the active device regions; and thermally cycling the base substrate and the first semiconductor layer such that the first semiconductor layer expands and contracts at a different rate than the base substrate, wherein the pair of tracks physically decouple adjacent ones of the active device regions during the thermal cycling. ### Claim 17 (depends on 16) The method of claim 16, wherein the pair of tracks crack during the thermal cycling, and wherein the cracks allow the active device regions to expand and contract at a different rate than the base substrate during the thermal cycling. ### Claim 18 (depends on 16) The method of claim 16, wherein the pair of tracks comprise polycrystalline regions of the second semiconductor material, and wherein the active device regions comprise monocrystalline regions of the second semiconductor material. ### Claim 19 (depends on 16) The method of claim 16, wherein the pair of tracks comprise amorphous regions of the second semiconductor material, and wherein the active device regions comprise monocrystalline regions of the second semiconductor material. ### Claim 20 A compound semiconductor substrate, comprising: a crystalline base substrate comprising: a first region that extends to a main surface of the base substrate and has a crystalline structure that is damaged and a second region that is adjacent the first region and has a crystalline structure that is undamaged; and a first semiconductor layer formed on the main surface and comprising a third region covering the first region of the base substrate and a fourth region of covering the second region of the base substrate, the third region having a crystalline structure that is disorganized relative to a crystalline structure of the fourth region, wherein the base substrate has a different coefficient of thermal expansion than the first semiconductor layer. ### Claim 21 (depends on 21) The compound semiconductor substrate of claim 21, wherein the third regions of the first semiconductor layer comprise cracks. ### Claim 22 (depends on 21) The compound semiconductor substrate of claim 21, wherein the third regions comprise polycrystalline or amorphous regions of the second semiconductor material, and wherein the active device regions comprise monocrystalline regions of the second semiconductor material. ### Claim 23 (depends on 20) The compound semiconductor substrate of claim 20, wherein the compound semiconductor substrate forms a semiconductor die comprising one or more semiconductor devices being formed in the fourth region, and wherein the third regions are disposed around a perimeter of the die. ### Claim 24 (depends on 20) The compound semiconductor substrate of claim 20, wherein the fourth regions occupy 50% of less than an overall area of semiconductor die, and wherein the fourth regions provide an active channel region for one or more HEMT devices.