# US 2017/0287643 A1 · Method of Producing Multi-Layer Ceramic Electronic Component and Multi-Layer Ceramic Electronic Component

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- Number: US 2017/0287643 A1
- Document ID: US20170287643A1
- Status: Published application
- Kind: A1
- Application number: 15/474,351
- Filed: 2017-03-30
- Published: 2017-10-05
- Earliest claimed: 2016-03-30
- Assignees: Taiyo Yuden Co., Ltd.
- Applicants: Taiyo Yuden Co., Ltd.
- Inventors: Joji Kobayashi; Toshimitsu Kogure; Yasunari Kato; Hidenori Wakayanagi; Yosuke Sato
- Web page: https://patentgrep.com/patent/US20170287643A1

## CPC

- H01G 4/30: Stacked capacitors (H01G4/33 takes precedence)
- H01G 4/12: Ceramic dielectrics {(H01G4/085 takes precedence)}
- H01G 4/224: Housing; Encapsulation
- H01G 4/232: electrically connecting two or more layers of a stacked or rolled capacitor
- H01G: CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE (selection of specified materials as dielectric H01B3/00; capacitors having potential barriers H10D1/62, H10K10/10)

## Abstract

A method of producing a multi-layer ceramic electronic component includes: preparing a multi-layer chip including ceramic layers laminated in a first axis direction, internal electrodes disposed between the ceramic layers, and a side surface on which the internal electrodes are exposed; applying a ceramic paste to the side surface; and pressing the applied ceramic paste toward the side surface to planarize the applied ceramic paste.

## Claims

### Claim 1

A method of producing a Multi-layer ceramic electronic component, the method comprising:
preparing a multi-layer chip including
ceramic layers laminated in a first axis direction,
internal electrodes disposed between the ceramic layers, and
a side surface on which the internal electrodes are exposed;
applying a ceramic paste to the side surface; and
pressing the applied ceramic paste toward the side surface to planarize the applied ceramic paste.

### Claim 2 (depends on 1)

The method of producing a multi-layer ceramic electronic component according to claim 1, wherein
the side surface is immersed in the ceramic paste to apply the ceramic paste to the side surface.

### Claim 3 (depends on 1)

The method of producing a multi-layer ceramic electronic component according to claim 1, wherein
the ceramic paste is pressed with a flat plate to planarize the ceramic paste.

### Claim 4 (depends on 3)

The method of producing a multi-layer ceramic electronic component according to claim 3, wherein
the flat plate includes a release layer on a surface of the flat plate, the release layer enhancing release properties of the ceramic paste.

### Claim 5 (depends on 1)

The method of producing a multi-layer ceramic electronic component according to claim 1, wherein
the ceramic paste is applied and then dried.

### Claim 6 (depends on 1)

The method of producing a multi-layer ceramic electronic component according to claim 1, wherein
a bulging portion of the ceramic paste is pressed to flow to a circumference of the ceramic paste, to planarize the ceramic paste.

### Claim 7 (depends on 6)

The method of producing a multi-layer ceramic electronic component according to claim 6, wherein
a length of the planarized portion along the first axis direction is 30% or more and 70% or less of a length of the multi-layer chip along the first axis direction.

### Claim 8 (depends on 6)

The method of producing a multi-layer ceramic electronic component according to claim 6, wherein
the ceramic paste is pressed in a second axis direction to be planarized, the second axis direction being orthogonal to the side surface, and
a length of the planarized portion along a third axis direction is 30% or more and 70% or less of a length of the multi-layer chip along the third axis direction, the third axis direction being orthogonal to the first axis direction and the second axis direction.

### Claim 9

A multi-layer ceramic electronic component, comprising:
a multi-layer chip including
ceramic layers laminated in a first axis direction,
internal electrodes disposed between the ceramic layers, and
a side surface on which the internal electrodes are exposed; and
a side margin that is made of dielectric ceramics and provided on the side surface, the side margin including
a flat portion having a predetermined thickness in a second axis direction, the second axis direction being orthogonal to the side surface, and
a circumferential portion that is formed around the flat portion and has a thickness smaller than the thickness of the flat portion in the second axis direction.

### Claim 10 (depends on 9)

The multi-layer ceramic electronic component according to claim 9, wherein
a length of the flat portion along the first axis direction is 30% or more and 70% or less of a length of the multi-layer chip along the first axis direction.

### Claim 11 (depends on 9)

The multi-layer ceramic electronic component according to claim 9, wherein
a length of the flat portion along a third axis direction is 30% or more and 70% or less of a length of the multi-layer chip along the third axis direction, the third axis direction being orthogonal to the first axis direction and the second axis direction.