# US 2017/0287564 A1 · Memory system and operating method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0287564 A1 - Document ID: US20170287564A1 - Status: Published application - Kind: A1 - Application number: 15/222,593 - Filed: 2016-07-28 - Published: 2017-10-05 - Earliest claimed: 2016-03-29 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Byoung Jun PARK; Seong Jo PARK - Web page: https://patentgrep.com/patent/US20170287564A1 ## CPC - G11C 16/26: Sensing or reading circuits; Data output circuits - G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature} - G11C 29/021: {in voltage or current generators} - G11C 29/028: {with adaption or trimming of parameters} - G11C 29/52: Protection of memory contents; Detection of errors in memory contents - G11C 7/04: with means for avoiding disturbances due to temperature effects - G11C 15/046: {using non-volatile storage elements} - G11C 2029/0409: {Online test} - G11C 2029/0411: {Online error correction} - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract The present disclosure relates to a memory system and an operating method thereof. A memory system may include a semiconductor memory device including a cam block and a normal memory block, and a controller suitable for setting an initial setting read voltage according to an option parameter stored in the cam block and controlling the semiconductor memory device to perform a first read operation to the normal memory block according to the initial setting read voltage. ## Claims ### Claim 1 A memory system, comprising: a semiconductor memory device including a cam block and a normal memory block; and a controller suitable for setting an initial setting read voltage according to an option parameter stored in the cam block, and controlling the semiconductor memory device to perform a first read operation to the normal memory block according to the initial setting read voltage. ### Claim 2 (depends on 1) The memory system of claim 1, wherein the option parameter includes temperature information of the semiconductor memory device, time information of a last performed read operation, and read count information. ### Claim 3 (depends on 1) The memory system of claim 1, wherein the controller sets the initial setting read voltage by selecting one among a plurality of initial setting read voltage indexes, and wherein the initial setting read voltage is set such that a number of error bits included in data read as a result of the first read operation is less than a maximum number of allowable error bits. ### Claim 4 (depends on 1) The memory system of claim 1, wherein the controller controls the semiconductor memory device to perform a second read operation according to a read retry scheme when a number of fail bits included in data read as a result of the first read operation is greater than a maximum number of allowable error bits. ### Claim 5 (depends on 4) The memory system of claim 4, wherein the second read operation is performed to the normal memory block according to a read voltage, with which a smallest number of error bits is detected while repeating a read operation to the normal memory block with gradual variation of the read voltage. ### Claim 6 (depends on 4) The memory system of claim 4, wherein the semiconductor memory device comprises: a memory cell array including the cam block and the normal memory block; a peripheral circuit suitable for performing a read operation to the normal memory block; and a control logic suitable for controlling the peripheral circuit to read the option parameter stored in the cam block, and output the option parameter to the controller. ### Claim 7 (depends on 6) The memory system of claim 6, wherein the control logic controls the peripheral circuit to perform the first read operation to the normal memory block according to the initial setting read voltage. ### Claim 8 (depends on 4) The memory system of claim 4, wherein the controller comprises: random access memory (RAM) suitable for storing firmware; an error correcting block suitable for detecting an error bit of data read from the semiconductor memory device, and correcting a detected error bit; and a processing unit suitable for controlling the semiconductor memory device to repeat a read operation to the normal memory block with gradual variation of the read voltage according to a read retry table and to control a read voltage of the second read operation according to an error detection result of the error correcting block when the number of fail bits included in data read as a result of the first read operation is greater than the maximum number of allowable error bits. ### Claim 9 (depends on 8) The memory system of claim 8, wherein the firmware includes a plurality of initial setting read voltage indexes. ### Claim 10 (depends on 9) The memory system of claim 9, wherein the processing unit selects one among the initial setting read voltage indexes according to the option parameter, and sets the initial setting read voltage according to the selected initial setting read voltage index. ### Claim 11 A memory system, comprising: a semiconductor memory device including a cam block and a normal memory block; and a controller suitable for setting an initial setting read voltage according to an option parameter stored in the cam block and a plurality of initial setting read voltage indexes, and controlling the semiconductor memory device to perform a first read operation to the normal memory block according to the initial setting read voltage. ### Claim 12 (depends on 11) The memory system of claim 11, wherein the option parameter includes temperature information of the semiconductor memory device, time information of a last performed read operation, and read count information. ### Claim 13 (depends on 11) The memory system of claim 11, wherein the controller sets the initial setting read voltage by selecting one among the plurality of initial setting read voltage indexes according to the option parameter. ### Claim 14 (depends on 13) The memory system of claim 13, wherein the controller sets the initial setting read voltage such that a number of error bits included in data read as a result of the first read operation is less than a maximum number of allowable error bits. ### Claim 15 (depends on 14) The memory system of claim 14, wherein the controller controls the semiconductor memory device to perform a second read operation according to a read retry scheme when a number of fail bits included in data read as the result of the first read operation is greater than a maximum number of allowable error bits. ### Claim 16 (depends on 15) The memory system of claim 15, wherein the second read operation is performed to the normal memory block according to a read voltage, with which a smallest number of error bits is detected while repeating a read operation to the normal memory block with gradual variation of the read voltage. ### Claim 17 A method of operating a memory system including a semiconductor memory device including a cam block and a normal memory block and a controller controlling a read operation of the semiconductor memory device, the method comprising: setting an initial setting read voltage according to an option parameter stored in the cam block when a read request is input to the controller; performing a first read operation according to the initial setting read voltage; and performing a second read operation according to a read retry scheme when a number of fail bits included in data read as a result of the first read operation is greater than a maximum number of allowable error bits. ### Claim 18 (depends on 17) The method of claim 17, wherein the option parameter includes temperature information of the semiconductor memory device, time information of a last performed read operation, and read count information. ### Claim 19 (depends on 17) The method of claim 17, wherein the setting of the initial setting read voltage comprises setting the initial setting read voltage by selecting one among a plurality of initial setting read voltage indexes stored in the controller or the cam block, and wherein the initial setting read voltage is set according to the option parameter such that a number of error bits included in data read as a result of the first read operation is less than a maximum number of allowable error bits. ### Claim 20 (depends on 17) The method of claim 17, wherein the second read operation is performed to the normal memory block according to a read voltage, with which a smallest number of error bits is detected while repeating a read operation to the normal memory block with gradual variation of the read voltage.