Multi-time programmable non-volatile memory cell and associated circuits

A multi-time programmable memory cell, comprising:

• a memory module, configured to store a data with a multi-time programmable capability;
• an erase module, configured to erase the data stored in the memory module based on an erase control signal;
• a write module, configured to store a first programming signal and a second programming signal into the memory module in accordance with a first programming control signal and a second programming control signal, wherein the first programming control signal and the second programming control signal are logically complementary, and the first programming signal and the second programming signal are logically complementary;
• a read module, configured to read out the data stored in the memory module and provide a first read signal and a second read signal accordingly based on a read control signal, wherein the first read signal and the second read signal are logically complementary;
• a load module, configured to provide a first load signal and a second load signal according to a first load control signal and a second load control signal, wherein the first load control signal and the second load control signal are logically complementary, and the first load signal and the second load signal are logically complementary;
• a latch module, configured to provide a first balance signal and a second balance signal in response in part to the first read signal and the second read signal, and in response in part to the first load signal and the second load signal;
• a balance module, configured to sample the first balance signal and the second balance signal and provide a sampled signal in response to the first balance signal and the second balance signal, wherein the sampled signal is being stored during when a first latch control signal is at a first state and the second latch control signal is at a second state, and wherein the sampled signal is being held during when the first latch control signal is in the second state and the second latch control signal is in the first state;
• and
• a single-ended output module, configured to provide an output signal in response to the sampled signal.

A circuit configured to achieve a function of a D flip-flop, comprising:

• a logic array, configured to receive a data signal and a clock signal, provide a first load control signal and a second load control signal based on the data signal, and provide a first latch control signal and a second latch control signal based on the clock signal;
• a differential multi-time programmable memory cell, coupled to the logic array to receive the first load control signal and the second load control signal, the differential multi-time programmable memory cell is configured to provide a first balance signal and a second balance signal in response to the first load control signal and the second load control signal via a load operation;
• and
• a second-level latch cell, coupled to the differential multi-time programmable memory cell to receive the first balance signal and the second balance signal, coupled to the logic array to receive the first latch control signal and the second latch control signal, configured to generate a sampled signal in response to the first balance signal and the second balance signal, and configured to provide an output signal in response to the sampled signal;
• wherein
• the sampled signal is being stored during when the first latch control signal is at a first state and the second latch control signal is at a second state;
• and wherein
• the sampled signal is being held during when the first latch control signal is in the second state and the first latch control signal is in the first state.

A circuit configured to achieve a function of a register, comprising:

• a sequence logic unit, configured to receive an address signal, a first signal comprising one of a clock signal and a request signal, and a reading-and-writing enable signal, and is configured to provide an enable control signal, a first latch control signal, a second latch control signal and a load enable signal based on the address signal, the first signal, and the reading-and-writing enable signal;
• a load logic unit, coupled to the sequence logic unit to receive the load enable signal and configured to receive a data signal, the load logic unit is configured to provide a first load control signal and a second load control signal based on the load enable signal and the data signal;
• a write logic unit, configured to receive a write signal and an output signal, and provide a first programming control signal and a second programming control signal based on the write signal and the output signal;
• a differential multi-time programmable memory cell, coupled to the sequence logic unit to receive the enable control signal, coupled to the load logic unit to receive the first load control signal and the second load control signal, coupled to the write logic unit to receive the first programming control signal and the second programming control signal, and the differential multi-time programmable memory cell is configured to provide a first balance signal and a second balance signal based on the enable control signal, the first load control signal, the second load control signal, the first programming control signal, and the second programming signal, wherein the differential multi-time programmable memory cell is capable to erase a stored data via an erase operation, store the data in response to the first programming control signal and the second programming control signal via a write operation, read out the stored data and provide the first balance signal and the second balance signal accordingly via a read operation, and load the first load control signal and the second load control signal and provide the first balance signal and the second balance signal accordingly via a load operation;
• and
• a second-level latch cell, coupled to the differential multi-time programmable memory cell to receive the first balance signal and the second balance signal, coupled to the sequence logic unit to receive the first latch control signal and the second latch control signal, configured to generate a sampled signal in response to the first balance signal and the second balance signal, and configured to provide the output signal based on the sampled signal;
• wherein
• the sampled signal is being stored during when the first latch control signal is at a first state and the second latch control signal is at a second state;
• and wherein
• the sampled signal is being held during when the first latch control signal is in the second state and the first latch control signal is in the first state.