# US 2017/0287558 A1 · Memristor-based processor integrating computing and memory and method for using the processor

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- Number: US 2017/0287558 A1
- Document ID: US20170287558A1
- Status: Published application
- Kind: A1
- Application number: 15/629,714
- Filed: 2017-06-21
- Published: 2017-10-05
- Earliest claimed: 2014-12-22
- Assignees: Huazhong University of Science and Technology
- Applicants: Huazhong University of Science and Technology
- Inventors: Qun LIU; Tao ZHANG; Xiangshui MIAO; Yi LI; Yaxiong ZHOU; Tianpeng MIAO
- Web page: https://patentgrep.com/patent/US20170287558A1

## CPC

- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites}
- G11C 13/0097: {Erasing, e.g. resetting, circuits or methods}
- G11C 2213/77: Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A processor including a computing and memory structure including X in number integration units and X in number communication units, and a control unit. The integration units are computing and memory units (CMUs), each computing and memory unit (CMU) is connected to a corresponding communication unit. The control unit is configured to produce control signals according to the commands, connect communication networks between the CMUs, choose operand addresses and result storage addresses, and search for one or a plurality of idle CMUs when extra CMUs are required for an operation. Each computing and memory unit includes M in number bit units and M−1 in number vertical line switches. Each bit unit includes a resistor, a horizontal line switch and N in number memristors. X is a positive integer greater than or equal to 2; M is a positive integer greater than or equal to 1.

## Claims

### Claim 1

A processor, comprising:
a computing and memory structure comprising X in number integration units and s, the integration units being computing and memory units (CMUs), each computing and memory unit (CMU) being connected to a corresponding communication unit, and the X in number communication units being mutually connected to form a communication network; and
a control unit, being configured to produce control signals according to commands, connect communication networks between the CMUs, choose operand addresses and result storage addresses, and search for one or a plurality of idle CMUs when extra CMUs are required for an operation;
wherein
each computing and memory unit comprises M in number bit units and M−1 in number vertical line switches; the M in number bit units comprise M in number bit lines which are all connected to one communication unit; and a vertical line switch, if exists, is arranged between bit line ends of two adjacent bit units;
each bit unit comprises a resistor, a horizontal line switch and N in number memristors; one end of a first memristor serves as a first selection line and the other end of the first memristor is grounded via a horizontal line switch and a resistor in series; one end of a second memristor serves as a second selection line and the other end of the second memristor is connected to the other end of the first memristor; one end of a third memristor serves as a third selection line and the other end of the third memristor is connected to the other end of the second memristor . . . one end of a Nth memristor serves as a Nth selection line and the other end of the Nth memristor is connected to the other end of a N−1th memristor; and
X is a positive integer greater than or equal to 2; M is a positive integer greater than or equal to 1; and N is a positive integer greater than or equal to 1.

### Claim 2 (depends on 1)

The processor of claim 1, wherein a resistance value of a resistor in a bit unit is far greater than a resistance value of a memristor in a low-resistance state and far less than a resistance value of the memristor in a high-resistance state.

### Claim 3 (depends on 1)

A method of data transmission of the processor of claim 1, comprising:
(1.1) applying a first voltage VCLEAR to selection lines of first set of memristors B1 and second set of memristors B2 in a second integration unit B-CMU; therefore, the memristors are in a state of high resistance, and the state of high resistance is marked as 0;
the first voltage VCLEAR is negative and greater than a first threshold voltage; the first threshold voltage is a voltage that changes the state of memristors;
(1.2) connecting a first integration unit A-CMU and the second integration unit B-CMU through a communication network; applying a second voltage VCOND to a selection line of a first set of memristors A1 of the first integration unit A-CMU, and applying a third voltage VSET to the selection line of the second set of memristors B2 of the second integration unit B-CMU, and storing ((NOT A1) OR B2) in the second set of memristors B2 to achieve implication operation;
the second voltage VCOND is positive and less than the threshold voltage; the third voltage VSET is positive and greater than the threshold voltage; a difference between the third voltage VSET and the second voltage VCOND is less than the threshold voltage; and
(1.3) applying the second voltage VCOND to the selection line of the second set of memristors B2 in the second integration unit B-CMU; and applying the third voltage VSET to the first set of memristors B1 in the second integration unit B-CMU; storing data in the first set of memristors B1 to realize implication operation B1←B2 IMP B1 so as to transmit data x in the first set of memristors A1 in the first integration unit A-CMU into the first set of memristors B1 in the second integration unit B-CMU.

### Claim 4 (depends on 1)

A method of data exchange of the processor of claim 1, comprising:
(2.1) applying a first voltage VCLEAR to selection lines of a first set of memristors C1 and a second set of memristors C2 of a third integration unit C-CMU, and to selection lines of a first set of memristors D1 and a second set of memristors D2 of a fourth integration unit D-CMU; therefore, C1, C2, D1 and D2 are in a state of high resistance and the state of high resistance is marked as 0;
(2.2) through a communication network, connecting a first integration unit A-CMU and the third integration unit C-CMU, and connecting a second integration unit B-CMU and the fourth integration unit D-CMU; applying a second voltage VCOND to selection lines of a first set of memristors A1 of the first integration unit A-CMU and a first set of memristors B1 of the second integration unit B-CMU simultaneously, and applying a third voltage VSET to the selection lines of a second set of memristors C2 of the third integration unit C-CMU and a second set of memristors D2 of the fourth integration unit D-CMU simultaneously; therefore, the implication operation of C2←A1 IMP C2 and D2←B1 IMP D2 is realized;
(2.3) applying the second voltage VCOND to selection lines of a second set of memristors C2 of the third integration unit C-CMU and a second set of memristors D2 of the fourth integration unit D-CMU simultaneously, and applying the third voltage VSET to the selection lines of a first set of memristors C1 of the third integration unit C-CMU and a first set of memristors D1 of the fourth integration unit D-CMU simultaneously; therefore, the implication operation of C1←C2 IMP C1 and D1←D2 IMP D1 is realized;
(2.4) applying the first voltage VCLEAR to the selection lines of a first set of memristors A1 of the first integration unit A-CMU, a second set of memristors A2 of the first integration unit A-CMU, a first set of memristors B1 of the second integration unit B-CMU and a second set of memristors B2 of the second integration unit B-CMU simultaneously; therefore, a first set of memristors A1 of the first integration unit A-CMU, a second set of memristors A2 of the first integration unit A-CMU, a first set of memristors B1 of the second integration unit B-CMU and a second set of memristors B2 of the second integration unit B-CMU are in a state of high resistance;
(2.5) through a communication network, connecting a first integration unit A-CMU and a fourth integration unit D-CMU, and connecting a second integration unit B-CMU and third integration unit C-CMU; applying the second voltage VCOND to the a first set of memristors C1 of the third integration unit C-CMU and a first set of memristors D1 of the fourth integration unit D-CMU simultaneously, and applying the third voltage VSET to the selection lines of a second set of memristors A2 of the first integration unit A-CMU and a second set of memristors B2 of the second integration unit B-CMU simultaneously; therefore, the implication operation of A2←D1 IMP A2 and B2←C1 IMP B2 is realized;
(2.6) applying the second voltage VCOND to the selection lines of a second set of memristors A2 of the first integration unit A-CMU and a second set of memristors B2 of the second integration unit B-CMU simultaneously, and applying the third voltage VSET to the selection lines of a first set of memristors A1 of the first integration unit A-CMU and a first set of memristors B1 of the second integration unit B-CMU simultaneously; therefore, the implication operation of A1←A2 IMP A1 and B1←B2 IMP B1 is realized, data x is stored in B1 of a second integration unit B-CMU and data y is stored in a first set of memristors A1 of the first integration unit A-CMU.

### Claim 5 (depends on 1)

A method of addition operation of the processor of claim 1, comprising:
(3.1) applying a first voltage VCLEAR to selection lines of a second set of memristors C2 of the third integration unit C-CMU, a first set of memristors G1 of the seventh integration unit G-CMU, a second set of memristors G2 of the seventh integration unit G-CMU, a second set of memristors D2 of the fourth integration unit D-CMU and a first set of memristors H1 of the eighth integration unit H-CMU; therefore, C2, G1, G2, D2 and H1 are in a state of high resistance;
(3.2) through a communication network, connecting a first integration unit A-CMU and a seventh integration unit G-CMU, and connecting a second integration unit B-CMU and an eighth integration unit H-CMU; applying a second voltage VCOND to selection lines of a first set of memristors A1 of the first integration unit A-CMU and a first set of memristors B1 of the second integration unit B-CMU simultaneously, and applying a third voltage VSET to the selection lines of a first set of memristors G1 of the seventh integration unit G-CMU and a first set of memristors H1 of the eighth integration unit H-CMU simultaneously; therefore, the implication operation of G1←A1 IMP G1 and H1←B1 IMP H1 is realized;
(3.3) through a communication network, connecting a third integration unit C-CMU and a seventh integration unit G-CMU, and connecting a fourth integration unit D-CMU and an eighth integration unit H-CMU; applying the second voltage VCOND to the selection lines of a first set of memristors G1 of the seventh integration unit G-CMU and a first set of memristors H1 of the eighth integration unit H-CMU simultaneously, and applying the third voltage VSET to the selection lines of a second set of memristors C2 of the third integration unit C-CMU and a second set of memristors D2 of the fourth integration unit D-CMU simultaneously; therefore, the implication operation of C2←G1 IMP C2 and D2←H1 IMP D2 is realized;
(3.4) through a communication network, connecting a first integration unit A-CMU and a fourth integration unit D-CMU, and connecting a second integration unit B-CMU and a third integration unit C-CMU; applying the second voltage VCOND to the selection lines of a first set of memristors A1 of the first integration unit A-CMU and a first set of memristors B1 of the second integration unit B-CMU simultaneously, and applying the third voltage VSET to the selection lines of a second set of memristors C2 of the third integration unit C-CMU and a second set of memristors D2 of the fourth integration unit D-CMU simultaneously; therefore, the implication operation of D2←A1 IMP D2 and C2←B1 IMP C2 is realized;
(3.5) through a communication network, connecting a third integration unit C-CMU and a seventh integration unit G-CMU; applying the second voltage VCOND to the selection line of a second set of memristors C2 of the third integration unit C-CMU, and applying the third voltage VSET to the selection line of G2; therefore, the implication operation of G2←C2 IMP G2 is realized;
(3.6) through a communication network, connecting a fourth integration unit D-CMU and a seventh integration unit G-CMU; applying the second voltage VCOND to the selection line of a second set of memristors D2 of the fourth integration unit D-CMU, and applying the third voltage VSET to the selection line of G2; therefore, the implication operation of G2←D2 IMP G2 is realized;
(3.7) applying the first voltage VCLEAR to the selection lines of an ith memristor B2, i of the second set of memristors of the second integration unit B-CMU, an ith memristor D2, i of the second set of memristors of the fourth integration unit D-CMU, and an (i+1)th memristor H2, i+1 of the second set of memristors of the eighth integration unit H-CMU simultaneously; therefore, B2, i, D2, i and H2, i+1 are in a state of high resistance, initially, i=1;
(3.8) through a communication network, connecting a fourth integration unit D-CMU and a seventh integration unit G-CMU; applying the second voltage VCOND to the selection lines of B1, i and G2, i, and applying the third voltage VSET to the selection lines of an ith memristor B2, i of the second set of memristors B2 of the second integration unit B-CMU and an ith memristor D2, i of the second set of memristors of the fourth integration unit D-CMU; therefore, the implication operation of B2, i←B1, i IMP B2, i and D2, i←G2, i IMP D2, i is realized;
(3.9) through a communication network, connecting a first integration unit A-CMU and a second integration unit B-CMU, and connecting a fourth integration unit D-CMU and an eighth integration unit H-CMU; applying the second voltage VCOND to the selection lines of A1, i and H2, i, and applying the third voltage VSET to the selection lines of an ith memristor B2, i of the second set of memristors B2 of the second integration unit B-CMU and an ith memristor D2, i of the second set of memristors of the fourth integration unit D-CMU; therefore, the implication operation of B2, i←A1, i IMP B2, i and D2, i←H2, i IMP D2, i is realized;
(3.10) through a communication network, connecting a fourth integration unit D-CMU and an eighth integration unit H-CMU; the switch DKi is turned off, and the switch DKi, i+1 is turned on; applying the second voltage VCOND to the selection line of an ith memristor D2, i of the second set of memristors of the fourth integration unit D-CMU, and applying the third voltage VSET to the selection line of H2, i+1; therefore, the implication operation of H2, i+1←D2, i IMP H2, i+1 is realized;
(3.11) through a communication network, connecting a second integration unit B-CMU and an eighth integration unit H-CMU; switches BKi, HKi, HKi+1 and BKi, i+1 are turned off, and the switch HKi, i+1 is turned on; applying the second voltage VCOND to the selection line of an ith memristor B2, i of the second set of memristors B2 of the second integration unit B-CMU, and applying the third voltage VSET to the selection line of H2, i+1; therefore, the implication operation of H2, i+1←B2, i IMP H2, i+1 is realized;
(3.12) determining if i is less than 8, execute i+1 and returns to 3.7; if i≧8, execute following steps;
(3.13) applying the first voltage VCLEAR to the selection lines of a second set of memristors A2 of the first integration unit A-CMU, E1, a second set of memristors B2 of the second integration unit B-CMU, F1 and a first set of memristors C1 of the third integration unit C-CMU simultaneously; therefore, a second set of memristors A2 of the first integration unit A-CMU, E1, a second set of memristors B2 of the second integration unit B-CMU, F1 and a first set of memristors C1 of the third integration unit C-CMU are in a state of high resistance;
(3.14) through a communication network, connecting a fifth integration unit E-CMU and a seventh integration unit G-CMU, and connecting a sixth integration unit F-CMU and an eighth integration unit H-CMU; applying the second voltage VCOND to the selection lines of G2 and H2, and applying the third voltage VSET to the selection lines of E1 and F1; therefore, the implication operation of E1←G2 IMP E1 and F1←H2 IMP F1 is realized;
(3.15) through a communication network, connecting a first integration unit A-CMU and a fifth integration unit E-CMU, and connecting a second integration unit B-CMU and an eighth integration unit H-CMU; applying the second voltage VCOND to the selection lines of E1 and F1, and applying the third voltage VSET to the selection lines of a second set of memristors A2 of the first integration unit A-CMU and a second set of memristors B2 of the second integration unit B-CMU; therefore, the implication operation of A2←E1 IMP A2 and B2←F1 IMP B2 is realized;
(3.16) through a communication network, connecting a first integration unit A-CMU and an eighth integration unit H-CMU, and connecting a second integration unit B-CMU and a seventh integration unit G-CMU; applying the second voltage VCOND to the selection lines of H2 and G2, and applying the third voltage VSET to the selection lines of a second set of memristors A2 of the first integration unit A-CMU and a second set of memristors B2 of the second integration unit B-CMU; therefore, the implication operation of A2←H2 IMP A2 and B2←G2 IMP B2 is realized;
(3.17) through a communication network, connecting a first integration unit A-CMU and a third integration unit C-CMU; applying the second voltage VCOND to the selection line of a second set of memristors A2 of the first integration unit A-CMU, and applying the third voltage VSET to the selection line of a first set of memristors C1 of the third integration unit C-CMU; therefore, the implication operation of C1←A2 IMP C1 is realized;
(3.18) through a communication network, connecting a second integration unit B-CMU and a third integration unit C-CMU; applying the second voltage VCOND to the selection line of a second set of memristors B2 of the second integration unit B-CMU, and applying the third voltage VSET to the selection line of a first set of memristors C1 of the third integration unit C-CMU; therefore, the implication operation of C1←B2 IMP C1 is realized, so as to add data X in the first set of memristors A1 in the first integration unit A-CMU to data Y in the first set of memristors B1 in the second integration unit a second integration unit B-CMU, and store in C1 of a third integration unit C-CMU.

### Claim 6 (depends on 1)

A method of immediate operand addition of the processor of claim 1, the immediate operand being 128, the method comprising:
(4.1) applying the voltage VSET to the selection line of a first memristor B1, 1 of a first set of memristors of a second integration unit B-CMU, and applying the voltage VCLEAR to the selection lines of 2nd-8th memristors B1, 2-B1, 8 of a first set of memristors of a second integration unit B-CMU, the immediate operand 128 is written in a first set of memristors B1 of the second integration unit B-CMU;
(4.2) applying a first voltage VCLEAR to the selection lines of a second set of memristors C2 of the third integration unit C-CMU, a first set of memristors G1 of the seventh integration unit G-CMU, a second set of memristors G2 of the seventh integration unit G-CMU, a second set of memristors D2 of the fourth integration unit D-CMU and a first set of memristors H1 of the eighth integration unit H-CMU; therefore, C2, G1, G2, D2 and H1 are in a state of high resistance;
(4.3) through a communication network, connecting a first integration unit A-CMU and a seventh integration unit G-CMU, and connecting a second integration unit B-CMU and an eighth integration unit H-CMU; applying a second voltage VCOND to the selection lines of A1 and a first set of memristors B1 of the second integration unit B-CMU simultaneously, and applying a third voltage VSET to the selection lines of a first set of memristors G1 of the seventh integration unit G-CMU and a first set of memristors H1 of the eighth integration unit H-CMU simultaneously; therefore, the implication operation of G1←A1 IMP G1 and H1←B1 IMP H1 is realized;
(4.4) through a communication network, connecting a third integration unit C-CMU and a seventh integration unit G-CMU, and connecting a fourth integration unit D-CMU and an eighth integration unit H-CMU; applying the second voltage VCOND to the selection lines of a first set of memristors G1 of the seventh integration unit G-CMU and a first set of memristors H1 of the eighth integration unit H-CMU simultaneously, and applying the third voltage VSET to the selection lines of a second set of memristors C2 of the third integration unit C-CMU and a second set of memristors D2 of the fourth integration unit D-CMU simultaneously; therefore, the implication operation of C2←G1 IMP C2 and D2←H1 IMP D2 is realized;
(4.5) through a communication network, connecting a first integration unit A-CMU and a fourth integration unit D-CMU, and connecting a second integration unit B-CMU and a third integration unit C-CMU; applying the second voltage VCOND to the selection lines of a first set of memristors A1 of the first integration unit A-CMU and a first set of memristors B1 of the second integration unit B-CMU simultaneously, and applying the third voltage VSET to the selection lines of a second set of memristors C2 of the third integration unit C-CMU and a second set of memristors D2 of the fourth integration unit D-CMU simultaneously; therefore, the implication operation of D2←A1 IMP D2 and C2←B1 IMP C2 is realized;
(4.6) through a communication network, connecting a third integration unit C-CMU and a seventh integration unit G-CMU; applying the second voltage VCOND to the selection line of a second set of memristors C2 of the third integration unit C-CMU, and applying the third voltage VSET to the selection line of G2; therefore, the implication operation of G2←C2 IMP G2 is realized;
(4.7) through a communication network, connecting a fourth integration unit D-CMU and a seventh integration unit G-CMU; applying the second voltage VCOND to the selection line of a second set of memristors D2 of the fourth integration unit D-CMU, and applying the third voltage VSET to the selection line of G2; therefore, the implication operation of G2←D2 IMP G2 is realized;
(4.8) applying the first voltage VCLEAR to the selection lines of an ith memristor B2, i of the second set of memristors B2 of the second integration unit B-CMU, an ith memristor D2, i of the second set of memristors of the fourth integration unit D-CMU and an (i+1)th memristor H2, i+1 of the second set of memristors of the eighth integration unit H-CMU simultaneously; therefore, B2, i, D2, i and H2, i+1 are in a state of high resistance, initially, i=1;
(4.9) through a communication network, connecting a fourth integration unit D-CMU and a seventh integration unit G-CMU; applying the second voltage VCOND to the selection lines of B1, i and G2, i, and applying the third voltage VSET to the selection lines of an ith memristor B2, i of the second set of memristors B2 of the second integration unit B-CMU and an ith memristor D2, i of the second set of memristors of the fourth integration unit D-CMU; therefore, the implication operation of B2, i←B1, i IMP B2, i and D2, i←G2, i IMP D2, i is realized;
(4.10) through a communication network, connecting a first integration unit A-CMU and a second integration unit B-CMU, and connecting a fourth integration unit D-CMU and an eighth integration unit H-CMU; applying the second voltage VCOND to the selection lines of A1, i and H2, i, and applying the third voltage VSET to the selection lines of an ith memristor B2, i of the second set of memristors B2 of the second integration unit B-CMU and an ith memristor D2, i of the second set of memristors of the fourth integration unit D-CMU; therefore, the implication operation of B2, i←A1, i IMP B2, i and D2, i←H2, i IMP D2, i is realized;
(4.11) through a communication network, connecting a fourth integration unit D-CMU and an eighth integration unit H-CMU; the switch DKi is turned off, and the switch DKi, i+1 is turned on; applying the second voltage VCOND to the selection line of an ith memristor D2, i of the second set of memristors of the fourth integration unit D-CMU, and applying the third voltage VSET to the selection line of H2, i+1; therefore, the implication operation of H2, i+1←D2, i IMP H2, i+1 is realized;
(4.12) through a communication network, connecting a second integration unit B-CMU and an eighth integration unit H-CMU; switches BKi, HKi, HKi+1 and BKi, i+1 are turned off, and the switch HKi, i+1 is turned on; applying the second voltage VCOND to the selection line of an ith memristor B2, i of the second set of memristors B2 of the second integration unit B-CMU, and applying the third voltage VSET to the selection line of H2, i+1; therefore, the implication operation of H2, i+1←B2, i IMP H2, i+1 is realized;
(4.13) if i is less than 8, execute i+1 and return to (4.8); if i≧8, execute following steps;
(4.14) applying the first voltage VCLEAR to the selection lines of a second set of memristors A2 of the first integration unit A-CMU, E1, B2, F1 and a first set of memristors C1 of the third integration unit C-CMU simultaneously; therefore, a second set of memristors A2 of the first integration unit A-CMU, E1, B2, F1 and a first set of memristors C1 of the third integration unit C-CMU are in a state of high resistance;
(4.15) through a communication network, connecting a fifth integration unit E-CMU and a seventh integration unit G-CMU, and connecting a sixth integration unit F-CMU and an eighth integration unit H-CMU; applying the second voltage VCOND to the selection lines of G2 and H2, and applying the third voltage VSET to the selection lines of E1 and F1; therefore, the implication operation of E1←G2 IMP E1 and F1←H2 IMP F1 is realized;
(4.16) through a communication network, connecting a first integration unit A-CMU and a fifth integration unit E-CMU, and connecting a second integration unit B-CMU and an eighth integration unit H-CMU; applying the second voltage VCOND to the selection lines of E1 and F12, and applying the third voltage VSET to the selection lines of a second set of memristors A2 of the first integration unit A-CMU and a second set of memristors B2 of the second integration unit B-CMU; therefore, the implication operation of A2←E1 IMP A2 and B2←F1 IMP B2 is realized;
(4.17) through a communication network, connecting a first integration unit A-CMU and an eighth integration unit H-CMU, and connecting a second integration unit B-CMU and a seventh integration unit G-CMU; applying the second voltage VCOND to the selection lines of H2 and G2, and applying the third voltage VSET to the selection lines of a second set of memristors A2 of the first integration unit A-CMU and a second set of memristors B2 of the second integration unit B-CMU; therefore, the implication operation of A2←H2 IMP A2 and B2←G2 IMP B2 is realized;
(4.18) through a communication network, connecting a first integration unit A-CMU and a third integration unit C-CMU; applying the second voltage VCOND to the selection line of a second set of memristors A2 of the first integration unit A-CMU, and applying the third voltage VSET to the selection line of a first set of memristors C1 of the third integration unit C-CMU; therefore, the implication operation of C1←A2 IMP C1 is realized;
(4.19) through a communication network, connecting a second integration unit B-CMU and a third integration unit C-CMU; applying the second voltage VCOND to the selection line of a second set of memristors B2 of the second integration unit B-CMU, and applying the third voltage VSET to the selection line of a first set of memristors C1 of the third integration unit C-CMU; therefore, the implication operation of C1←B2 IMP C1 is realized.

### Claim 7 (depends on 1)

A method of logic AND of the processor of claim 1, comprising:
(5.1) applying a first voltage VCLEAR to the selection lines of a first set of memristors C1 of the third integration unit C-CMU and a second set of memristors C2 of the third integration unit C-CMU simultaneously; a first set of memristors C1 of the third integration unit C-CMU and a second set of memristors C2 of the third integration unit C-CMU are in a state of high resistance;
(5.2) through a communication network, connecting a second integration unit B-CMU and a third integration unit C-CMU; applying a second voltage VCOND to the selection line of a first set of memristors B1 of the second integration unit B-CMU, and applying a third voltage VSET to the selection line of a second set of memristors C2 of the third integration unit C-CMU; therefore, the implication operation of C2←B1 IMP C2 is realized;
(5.3) through a communication network, connecting a first integration unit A-CMU and a third integration unit C-CMU; applying the second voltage VCOND to the selection line of a first set of memristors A1 of the first integration unit A-CMU, and applying the third voltage VSET to the selection line of a second set of memristors C2 of the third integration unit C-CMU; therefore, the implication operation of C2←A1 IMP C2 is realized; and
(5.4) applying the second voltage VCOND to the selection line of a second set of memristors C2 of the third integration unit C-CMU, and applying the third voltage VSET to the selection line of a first set of memristors C1 of the third integration unit C-CMU; therefore, the implication operation of C1←C2 IMP C1 is realized.

### Claim 8 (depends on 1)

A method of logic OR of the processor of claim 1, comprising:
(6.1) applying a first voltage VCLEAR to the selection lines of a first set of memristors C1 of the third integration unit C-CMU, a second set of memristors C2 of the third integration unit C-CMU and a second set of memristors A2 of the first integration unit A-CMU simultaneously; therefore, a first set of memristors C1 of the third integration unit C-CMU, a second set of memristors C2 of the third integration unit C-CMU and a second set of memristors A2 of the first integration unit A-CMU are in a state of high resistance;
(6.2) through a communication network, connecting a second integration unit B-CMU and a third integration unit C-CMU; applying a second voltage VCOND to the selection line of a first set of memristors B1 of the second integration unit B-CMU, and applying a third voltage VSET to the selection line of a second set of memristors C2 of the third integration unit C-CMU; therefore, the implication operation of C2←B1 IMP C2 is realized;
(6.3) applying the second voltage VCOND to the selection line of a second set of memristors C2 of the third integration unit C-CMU, and applying the third voltage VSET to the selection line of a first set of memristors C1 of the third integration unit C-CMU; therefore, the implication operation of C1←C2 IMP C1 is realized;
(6.4) applying the second voltage VCOND to the selection line of A1, and applying the third voltage VSET to the selection line of a second set of memristors A2 of the first integration unit A-CMU; therefore, the implication operation of A2←A1 IMP A2 is realized; and
(6.5) through a communication network, connecting a first integration unit A-CMU and a third integration unit C-CMU; applying the second voltage VCOND to the selection line of a second set of memristors A2 of the first integration unit A-CMU, and applying the third voltage VSET to the selection line of a first set of memristors C1 of the third integration unit C-CMU; therefore, the implication operation of C1←A2 IMP C1 is realized.

### Claim 9 (depends on 1)

A method of logic NOT of the processor of claim 1, comprising:
(7.1) applying a first voltage VCLEAR to the selection line of a second set of memristors A2 of the first integration unit A-CMU; therefore, a second set of memristors A2 of the first integration unit A-CMU is in a state of high resistance; and
(7.2) applying a second voltage VCOND to the selection line of a first set of memristors A1 of the first integration unit A-CMU, and applying a third voltage VSET to the selection line of a second set of memristors A2 of the first integration unit A-CMU; therefore, the implication operation A2←A1 IMP A2 is realized

### Claim 10 (depends on 1)

A method of logic XOR of the processor of claim 1, comprising:
(8.1) applying a first voltage VCLEAR to the selection lines of a first set of memristors C1 of the third integration unit C-CMU, a second set of memristors C2 of the third integration unit C-CMU, a second set of memristors A2 of the first integration unit A-CMU, D1 and a second set of memristors D2 of the fourth integration unit D-CMU simultaneously; therefore, a first set of memristors C1 of the third integration unit C-CMU, a second set of memristors C2 of the third integration unit C-CMU, a second set of memristors A2 of the first integration unit A-CMU, D1 and D2 are in a state of high resistance;
(8.2) through a communication network, connecting a second integration unit B-CMU and a fourth integration unit D-CMU; applying a second voltage VCOND to the selection lines of A1 and a first set of memristors B1 of the second integration unit B-CMU simultaneously, and applying a third voltage VSET to the selection lines of a second set of memristors A2 of the first integration unit A-CMU and a second set of memristors D2 of the fourth integration unit D-CMU simultaneously; therefore, the implication operation of A2←A1 IMP A2 and D2←B1 IMP D2 is realized;
(8.3) through a communication network, connecting a first integration unit A-CMU and a third integration unit C-CMU; applying the second voltage VCOND to the selection lines of a second set of memristors A2 of the first integration unit A-CMU and a second set of memristors D2 of the fourth integration unit D-CMU simultaneously, and applying the third voltage VSET to the selection lines of a second set of memristors C2 of the third integration unit C-CMU and D1 simultaneously; therefore, the implication operation of C2←A2 IMP C2 and D2←D1 IMP D2 is realized;
(8.4) through a communication network, connecting a first integration unit A-CMU and a fourth integration unit D-CMU, and connecting a second integration unit B-CMU and a third integration unit C-CMU; applying the second voltage VCOND to the selection lines of a first set of memristors A1 of the first integration unit A-CMU and a first set of memristors B1 of the second integration unit B-CMU simultaneously, and applying the third voltage VSET to the selection lines of a second set of memristors C2 of the third integration unit C-CMU and D1 simultaneously; therefore, the implication operation of D1←A1 IMP D1 and C2←B1 IMP C2 is realized;
(8.5) through a communication network, connecting a second integration unit B-CMU and a third integration unit C-CMU; applying the second voltage VCOND to the selection line of a second set of memristors C2 of the third integration unit C-CMU, and applying the third voltage VSET to the selection line of a first set of memristors C1 of the third integration unit C-CMU; therefore, the implication operation of C1←C2 IMP C1 is realized;
(8.6) through a communication network, connecting a third integration unit C-CMU and a fourth integration unit D-CMU; applying the second voltage VCOND to the selection line of D1, and applying the third voltage VSET to the selection line of a first set of memristors C1 of the third integration unit C-CMU; therefore, the implication operation of C1←D1 IMP C1 is realized.

### Claim 11 (depends on 1)

A method of logic XOR of the processor of claim 1, comprising:
(9.1) applying a first voltage VCLEAR to the selection lines of a first set of memristors C1 of the third integration unit C-CMU, a second set of memristors C2 of the third integration unit C-CMU, a second set of memristors A2 of the first integration unit A-CMU and a second set of memristors B2 of the second integration unit B-CMU simultaneously; therefore, a first set of memristors C1 of the third integration unit C-CMU, a second set of memristors C2 of the third integration unit C-CMU, a second set of memristors A2 of the first integration unit A-CMU and a second set of memristors B2 of the second integration unit B-CMU are in a state of high resistance;
(9.2) through a communication network, connecting a second integration unit B-CMU and a third integration unit C-CMU; applying a second voltage VCOND to the selection line of a first set of memristors B1 of the second integration unit B-CMU, and applying a third voltage VSET to the selection line of a second set of memristors C2 of the third integration unit C-CMU; therefore, the implication operation of C2←B1 IMP C2 is realized;
(9.3) through a communication network, connecting a second integration unit B-CMU and a third integration unit C-CMU; applying the second voltage VCOND to the selection line of a second set of memristors C2 of the third integration unit C-CMU, and applying the third voltage VSET to the selection line of a second set of memristors B2 of the second integration unit B-CMU; therefore, the implication operation of B2←C2 IMP B2 is realized;
(9.4) applying the second voltage VCOND to the selection line of A1, and applying the third voltage VSET to the selection line of a second set of memristors A2 of the first integration unit A-CMU; therefore, the implication operation of A2←A1 IMP A2 is realized;
(9.5) through a communication network, connecting a first integration unit A-CMU and a second integration unit B-CMU; applying the second voltage VCOND to the selection line of a second set of memristors A2 of the first integration unit A-CMU, and applying the third voltage VSET to the selection line of a second set of memristors B2 of the second integration unit B-CMU; therefore, the implication operation of B2←A2 IMP B2 is realized;
(9.6) through a communication network, connecting a second integration unit B-CMU and a third integration unit C-CMU; applying the second voltage VCOND to the selection line of a second set of memristors B2 of the second integration unit B-CMU, and applying the third voltage VSET to the selection line of a first set of memristors C1 of the third integration unit C-CMU; therefore, the implication operation of C1←B2 IMP C1 is realized.

### Claim 12 (depends on 1)

A method of immediate operand AND of the processor of claim 1, the immediate operand being 128, the method comprising:
(10.1) applying a third voltage VSET to the selection line of a first memristor B1, 1 of first set of memristors of a second integration unit B-CMU, and applying a first voltage VCLEAR to the selection lines of 2nd-8th memristors B1, 2-B1, 8 of first set of memristors of a second integration unit B-CMU simultaneously; the operand 128 is written in a first set of memristors B1 of the second integration unit B-CMU;
(10.2) applying the first voltage VCLEAR to the selection lines of a first set of memristors C1 of the third integration unit C-CMU and a second set of memristors C2 of the third integration unit C-CMU; therefore, a first set of memristors C1 of the third integration unit C-CMU and a second set of memristors C2 of the third integration unit C-CMU are in a state of high resistance;
(10.3) through a communication network, connecting a second integration unit B-CMU and a third integration unit C-CMU; applying a second voltage VCOND to the selection line of a first set of memristors B1 of the second integration unit B-CMU, and applying the third voltage VSET to the selection line of a second set of memristors C2 of the third integration unit C-CMU; therefore, the implication operation of C2←B1 IMP C2 is realized;
(10.4) through a communication network, connecting a first integration unit A-CMU and a third integration unit C-CMU; applying the second voltage VCOND to the selection line of a first set of memristors A1 of the first integration unit A-CMU, and applying the third voltage VSET to the selection line of a second set of memristors C2 of the third integration unit C-CMU; therefore, the implication operation of C2←A1 IMP C2 is realized;
(10.5) applying the second voltage VCOND to the selection line of a second set of memristors C2 of the third integration unit C-CMU, and applying the third voltage VSET to the selection line of a first set of memristors C1 of the third integration unit C-CMU; therefore, the implication operation of C1←C2 IMP C1 is realized.

### Claim 13 (depends on 1)

A method of immediate operand OR of the processor of claim 1, the immediate operand being 128, and the method comprising:
(11.1) applying a third voltage VSET to the selection line of a first memristor B1, 1 of first set of memristors of a second integration unit B-CMU, and applying a first voltage VCLEAR to the selection lines of 2nd-8th memristors B1, 2-B1, 8 of first set of memristors of a second integration unit B-CMU simultaneously; the operand 128 is written in a first set of memristors B1 of the second integration unit B-CMU;
(11.2) applying the first voltage VCLEAR to the selection lines of a first set of memristors C1 of the third integration unit C-CMU, a second set of memristors C2 of the third integration unit C-CMU and a second set of memristors A2 of the first integration unit A-CMU simultaneously; therefore, a first set of memristors C1 of the third integration unit C-CMU, a second set of memristors C2 of the third integration unit C-CMU and a second set of memristors A2 of the first integration unit A-CMU are in a state of high resistance;
(11.3) through a communication network, connecting a second integration unit B-CMU and a third integration unit C-CMU; applying a second voltage VCOND to the selection line of a first set of memristors B1 of the second integration unit B-CMU, and applying the third voltage VSET to the selection line of a second set of memristors C2 of the third integration unit C-CMU; therefore, the implication operation of C2←B1 IMP C2 is realized;
(11.4) applying the second voltage VCOND to the selection line of a second set of memristors C2 of the third integration unit C-CMU, and applying the third voltage VSET to the selection line of a first set of memristors C1 of the third integration unit C-CMU; therefore, the implication operation of C1←C2 IMP C1 is realized;
(11.5) applying the second voltage VCOND to the selection line of a first set of memristors A1 of the first integration unit A-CMU, and applying the third voltage VSET to the selection line of a second set of memristors A2 of the first integration unit A-CMU; therefore, the implication operation of A2←A1 IMP A2 is realized;
(11.6) through a communication network, connecting a first integration unit A-CMU and a third integration unit C-CMU; applying the second voltage VCOND to the selection line of a second set of memristors A2 of the first integration unit A-CMU, and applying the third voltage VSET to the selection line of a first set of memristors C1 of the third integration unit C-CMU; therefore, the implication operation of C1←A2 IMP C1 is realized.

### Claim 14 (depends on 1)

A method of immediate operand XOR of the processor of claim 1, the immediate operand being 128, and the method comprising:
(12.1) applying a third voltage VSET to the selection line of a first memristor B1, 1 of first set of memristors of a second integration unit B-CMU, and applying a first voltage VCLEAR to the selection lines of 2nd-8th memristors B1, 2-B1, 8 of first set of memristors of a second integration unit B-CMU; the immediate operand 128 is written in a first set of memristors B1 of the second integration unit B-CMU;
(12.2) applying the first voltage VCLEAR to the selection lines of a first set of memristors C1 of the third integration unit C-CMU, a second set of memristors C2 of the third integration unit C-CMU, a second set of memristors A2 of the first integration unit A-CMU, D1 and a second set of memristors D2 of the fourth integration unit D-CMU simultaneously; therefore, a first set of memristors C1 of the third integration unit C-CMU, a second set of memristors C2 of the third integration unit C-CMU, a second set of memristors A2 of the first integration unit A-CMU, D1 and D2 are in a state of high resistance;
(12.3) through a communication network, connecting a second integration unit B-CMU and a fourth integration unit D-CMU; applying a second voltage VCOND to the selection lines of A1 and a first set of memristors B1 of the second integration unit B-CMU simultaneously, and applying the third voltage VSET to the selection lines of a second set of memristors A2 of the first integration unit A-CMU and a second set of memristors D2 of the fourth integration unit D-CMU simultaneously; therefore, the implication operation of A2←A1 IMP A2 and D2←B1 IMP D2 is realized;
(12.4) through a communication network, connecting a first integration unit A-CMU and a third integration unit C-CMU; applying the second voltage VCOND to the selection lines of a second set of memristors A2 of the first integration unit A-CMU and a second set of memristors D2 of the fourth integration unit D-CMU simultaneously, and applying the third voltage VSET to the selection lines of a second set of memristors C2 of the third integration unit C-CMU and D1 simultaneously; therefore, the implication operation of C2←A2 IMP C2 and D2←D1 IMP D2 is realized;
(12.5) through a communication network, connecting a first integration unit A-CMU and a fourth integration unit D-CMU, and connecting a second integration unit B-CMU and a third integration unit C-CMU; applying the second voltage VCOND to the selection lines of a first set of memristors A1 of the first integration unit A-CMU and a first set of memristors B1 of the second integration unit B-CMU simultaneously, and applying the third voltage VSET to the selection lines of a second set of memristors C2 of the third integration unit C-CMU and D1 simultaneously; therefore, the implication operation of D1←A1 IMP D1 and C2←B1 IMP C2 is realized;
(12.6) through a communication network, connecting a second integration unit B-CMU and a third integration unit C-CMU; applying the second voltage VCOND to the selection line of a second set of memristors C2 of the third integration unit C-CMU, and applying the third voltage VSET to the selection line of a first set of memristors C1 of the third integration unit C-CMU; therefore, the implication operation of C1←C2 IMP C1 is realized; and
(12.7) through a communication network, connecting a third integration unit C-CMU and a fourth integration unit D-CMU; applying the second voltage VCOND to the selection line of D1, and applying the third voltage VSET to the selection line of a first set of memristors C1 of the third integration unit C-CMU; therefore, the implication operation of C1←D1 IMP C1 is realized.

### Claim 15 (depends on 1)

A method of shift left by m Bits of the processor of claim 1, the method comprising:
(13.1) applying a first voltage VCLEAR to the selection lines of a first set of memristors C1 of the third integration unit C-CMU and a second set of memristors C2 of the third integration unit C-CMU; therefore, a first set of memristors C1 of the third integration unit C-CMU and a second set of memristors C2 of the third integration unit C-CMU are in a state of high resistance;
(13.2) through a communication network, connecting a first integration unit A-CMU and a third integration unit C-CMU, and A1, i+m=C1, i; the switch CK1 is turned off; applying a second voltage VCOND to the selection line of a first set of memristors A1 of the first integration unit A-CMU, and applying a third voltage VSET to the selection line of a second set of memristors C2 of the third integration unit C-CMU; therefore, the implication operation of C2←A1 IMP C2 is realized; and
(13.3) the switch CK1 is turned off; applying the second voltage VCOND to the selection line of a second set of memristors C2 of the third integration unit C-CMU, and applying the third voltage VSET to the selection line of a first set of memristors C1 of the third integration unit C-CMU; therefore, the implication operation of C1←C2 IMP C1 is realized.

### Claim 16 (depends on 1)

A method of shift left by m Bits of the processor of claim 1, the method comprising:
(14.1) applying a first voltage VCLEAR to the selection lines of a first set of memristors C1 of the third integration unit C-CMU and a second set of memristors C2 of the third integration unit C-CMU; therefore, a first set of memristors C1 of the third integration unit C-CMU and a second set of memristors C2 of the third integration unit C-CMU are in a state of high resistance;
(14.2) through a communication network, connecting a first integration unit A-CMU and a third integration unit C-CMU, and A1, i+m=C1, i; the switch CK1 is turned off; applying a second voltage VCOND to the selection line of a first set of memristors A1 of the first integration unit A-CMU, and applying a third voltage VSET to the selection line of a second set of memristors C2 of the third integration unit C-CMU; therefore, the implication operation of C2←A1 IMP C2 is realized; and
(14.3) the switch CK1 is turned off; applying the second voltage VCOND to the selection line of a second set of memristors C2 of the third integration unit C-CMU, and applying the third voltage VSET to the selection line of a first set of memristors C1 of the third integration unit C-CMU; therefore, the implication operation of C1←C2 IMP C1 is realized.