# US 2017/0287553 A1 · Semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0287553 A1 - Document ID: US20170287553A1 - Status: Published application - Kind: A1 - Application number: 15/627,535 - Filed: 2017-06-20 - Published: 2017-10-05 - Earliest claimed: 2015-09-11 - Assignees: Renesas Electronics Corporation - Applicants: Renesas Electronics Corporation - Inventors: Yuichiro ISHII - Web page: https://patentgrep.com/patent/US20170287553A1 ## CPC - G11C 11/419: Read-write [R-W] circuits - G11C 11/418: Address circuits - H10B 10/12: {comprising a MOSFET load element} - H10B 10/18: {Peripheral circuit regions} - H10D 89/10: Integrated device layouts - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract An assist driver is coupled to an end of a word line to which a word line driver is not coupled, and couples the other end of the word line to a first power source, in accordance with a voltage of the other end of the word line. ## Claims ### Claim at position 1 1-15. (canceled) ### Claim 16 A semiconductor device comprising: a memory array which includes a plurality of memory cells arranged in a matrix; word lines which are provided and correspond respectively to rows of the memory array; word line drivers which are coupled to ends of the word lines, and activate the word lines by coupling the one ends of the word lines to a first power source, when a corresponding row is selected; and assist drivers which are coupled to other ends of the word lines, and couple the other ends of the word lines to the first power source in accordance with a voltage of the other ends of the word lines, wherein each of the assist drivers receives a control signal pulse, and wherein the control signal pulse is transmitted to the assist drivers through a signal wiring. ### Claim 17 (depends on 16) The semiconductor device according to claim 16, wherein each of the assist drivers includes a PMOS transistor provided between a power source and the other end of each of the word lines. ### Claim 18 (depends on 17) The semiconductor device according to claim 17, wherein each of the assist drivers includes a NAND circuit, having one input coupled to the other end of the word line, other input receiving a control signal pulse, and an output coupled to a gate of the PMOS transistor. ### Claim 19 (depends on 16) The semiconductor device according to claim 16, wherein the control signal pulse is at a high level in a period since a rising start time of the word line until a voltage of the other end of the word line reaches a voltage of the first power source, and the pulse is at a low level in a period since a falling start time of the word line until the voltage of the other end of the word line reaches a ground voltage. ### Claim 20 (depends on 16) The semiconductor device according to claim 16, wherein the signal wiring is arranged on an outside of the memory array, in a direction horizontal to a substrate where the semiconductor device is implemented, and wherein the control signal pulse is commonly shared by a plurality of assist drivers coupled to the other ends of their corresponding word lines. ### Claim 21 (depends on 20) The semiconductor device according to claim 20, further comprising: a control circuit including a row decoder, wherein the row decoder generates a row selection signal in accordance with a row address signal to drive the address-designated word line WL into a selection state, and wherein the signal line is electrically connected to the control circuit to transmit the control signal from the control circuit to the assist drivers. ### Claim 22 (depends on 20) The semiconductor device according to claim 20, wherein the signal line extends in a direction parallel to the word line. ### Claim 23 (depends on 20) The semiconductor device according to claim 20, wherein a width of the signal line is larger than a width of the word line. ### Claim 24 (depends on 16) The semiconductor device according to claim 16, wherein each of the memory cells is an SRAM. ### Claim 25 (depends on 24) The semiconductor device according to claim 24, wherein each of the memory cells is a laterally long cell. ### Claim 26 (depends on 24) The semiconductor device according to claim 24, further comprising: a bit line pair which is provided and corresponds to each of columns of the memory array, wherein the memory cell includes: a first load transistor electrically coupled between a first power node and a first node; a first drive transistor electrically coupled between the first node and a second power node; a first access transistor electrically coupled between the first node and one of the bit line pairs; a second load transistor electrically coupled between the first power node and a second node; a second drive transistor electrically coupled between the second node and the second power node; a second access transistor electrically coupled between the second node and the other bit line of the bit line pairs; a first and a second P-well; an N-well; and a first to fourth active regions, wherein the N-well is arranged between the first and the second P-well to be adjacent to each other, wherein the second and third active regions are formed on the N-well, wherein the first and fourth active regions are formed on the first and second P-wells respectively, wherein the second active region is arranged between the first and third active regions, wherein the third active region is arranged between the second and fourth active regions, wherein the first drive transistor and the first access transistor are formed on the first active region, wherein the first load transistor is formed on the second active region, wherein the second load transistor is formed on the third active region, wherein the second access transistor and the second drive transistor are formed on the fourth active region, wherein gate electrodes of the first load transistor and the first drive transistor are formed of a first metal line, and wherein gate electrodes of the second load transistor and the second drive transistor are formed of the second metal line. ### Claim 27 (depends on 16) The semiconductor device according to claim 16, further comprising: a bit line pair which is provided and corresponds to columns of the memory array, wherein an output unit is coupled to the bit line pair of a plurality of adjacent columns, and outputs a voltage in accordance with written data to a bit line pair of a selected column from the adjacent columns, at time of writing data to the memory cell. ### Claim 28 (depends on 16) The semiconductor device according to claim 16, further comprising: a bit line pair which is arranged and corresponds to the columns of the memory array; and a sense amplifier which is coupled to a bit line pair of adjacent columns, and amplifies a voltage of a bit line pair of a selected column from the adjacent columns, at time of reading data from the memory cell. ### Claim 29 A semiconductor device comprising: a memory array which includes a plurality of memory cells arranged in a matrix; word lines which are provided and correspond respectively to rows of the memory array; a bit line pair which is provided and corresponds to columns of the memory array; word line drivers which are coupled to ends of the word lines, and activate the word lines by coupling the one ends of the word lines to a first power source, when a corresponding row is selected; and assist drivers which are coupled to other ends of the word lines, and couple the other ends of the word lines to the first power source in accordance with a voltage of the other ends of the word lines, wherein each of the assist drivers includes: a PMOS transistor provided between a power source and the other end of each of the word lines; and a delay circuit coupled to the other end of the word line and a NAND circuit having one input coupled to the other end of the word line, other input receiving an output of the delay circuit, and an output coupled to the gate of the PMOS transistor, wherein the memory cell includes: a first load transistor electrically coupled between a first power node and a first node; a first drive transistor electrically coupled between the first node and a second power node; a first access transistor electrically coupled between the first node and one of the bit line pairs; a second load transistor electrically coupled between the first power node and a second node; a second drive transistor electrically coupled between the second node and the second power node; a second access transistor electrically coupled between the second node and the other bit line of the bit line pairs; a first and a second P-well; an N-well; and a first to fourth active regions, wherein the N-well is arranged between the first and the second P-well to be adjacent to each other, wherein the second and third active regions are formed on the N-well, wherein the first and fourth active regions are formed on the first and second P-wells respectively, wherein the second active region is arranged between the first and third active regions, wherein the third active region is arranged between the second and fourth active regions, wherein the first drive transistor and the first access transistor are formed on the first active region, wherein the first load transistor is formed on the second active region, wherein the second load transistor is formed on the third active region, wherein the second access transistor and the second drive transistor are formed on the fourth active region, wherein gate electrodes of the first load transistor and the first drive transistor are formed of a first metal line, and wherein gate electrodes of the second load transistor and the second drive transistor are formed of the second metal line.