# US 2017/0287550 A1 · Leakage-aware activation control of a delayed keeper circuit for a dynamic read operation in a memory bit cell

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- Number: US 2017/0287550 A1
- Document ID: US20170287550A1
- Status: Published application
- Kind: A1
- Application number: 15/085,187
- Filed: 2016-03-30
- Published: 2017-10-05
- Earliest claimed: 2016-03-30
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Francois Ibrahim Atallah; Hoan Huu Nguyen; Keith Alan Bowman
- Web page: https://patentgrep.com/patent/US20170287550A1

## CPC

- G11C 11/419: Read-write [R-W] circuits
- G11C 7/06: Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits}
- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
- G11C 8/10: Decoders
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

Leakage-aware activation control of a delayed keeper circuit for a dynamic read operation in a memory bit cell is disclosed. In one aspect, a leakage-aware activation control circuit is provided for a dynamic read circuit configured to perform read operations on a memory bit cell. To prevent or mitigate contention between the delayed keeper circuit and a read port circuit in the dynamic read circuit pulling a dynamic node to opposite voltage levels when a read operation is initiated, the leakage-aware activation control circuit is configured to adaptively control activation timing of the delayed keeper circuit based on a comparison of N-type Field-Effect Transistor (NFET) leakage current to P-type FET (PFET) leakage current. In this manner, the leakage-aware activation control circuit can adaptively adjust the activation timing of the delayed keeper circuit based on the actual relative strengths of NFETs and PFETs.

## Claims

### Claim 1

A leakage-aware activation control circuit for controlling activation of a delayed keeper circuit in a dynamic read circuit for a memory bit cell, comprising:
an N-type Field-Effect Transistor (NFET) leakage circuit configured to provide an NFET leakage indicator indicating leakage current of at least one NFET in a dynamic read circuit;
a P-type Field-Effect Transistor (PFET) leakage circuit configured to provide a PFET leakage indicator indicating leakage current of at least one PFET in the dynamic read circuit;
a comparator circuit configured to:
receive the NFET leakage indicator and the PFET leakage indicator;
compare the NFET leakage indicator to the PFET leakage indicator; and
generate a FET leakage signal based on the comparison of the NFET leakage indicator to the PFET leakage indicator; and
a control signal generator configured to adaptively generate at least one control signal based on the FET leakage signal to control activation timing of a delayed keeper circuit.

### Claim 2 (depends on 1)

The leakage-aware activation control circuit of claim 1, wherein:
the NFET leakage circuit is configured to dynamically provide the NFET leakage indicator indicating the leakage current of the at least one NFET in the dynamic read circuit during operation of the dynamic read circuit; and
the PFET leakage circuit is configured to dynamically provide the PFET leakage indicator indicating the leakage current of the at least one PFET in the dynamic read circuit during operation of the dynamic read circuit.

### Claim 3 (depends on 1)

The leakage-aware activation control circuit of claim 1, wherein:
the NFET leakage circuit comprises an NFET leakage sensor configured to determine NFET leakage;
the NFET leakage sensor configured to provide the NFET leakage indicator indicating the leakage current of the at least one NFET based on the determined NFET leakage in the dynamic read circuit; and
the PFET leakage circuit comprises a PFET leakage sensor configured to determine PFET leakage;
the PFET leakage sensor configured to provide the PFET leakage indicator indicating the leakage current of the at least one PFET based on the determined PFET leakage in the dynamic read circuit.

### Claim 4 (depends on 3)

The leakage-aware activation control circuit of claim 3, wherein:
the NFET leakage sensor is comprised of at least one deactivated NFET configured to provide an NFET leakage current indicative of the leakage current of the at least one NFET; and
the PFET leakage sensor is comprised of at least one deactivated PFET configured to provide a PFET leakage current indicative of the leakage current of the at least one PFET.

### Claim 5 (depends on 4)

The leakage-aware activation control circuit of claim 4, wherein:
the NFET leakage sensor is further comprised of an NFET ring oscillator circuit comprising a plurality of first buffer circuits coupled together in a ring oscillator, each of the plurality of first buffer circuits configured to be activated by the NFET leakage current indicative of the leakage current of the at least one NFET from the at least one deactivated NFET, the NFET ring oscillator circuit configured to update the NFET leakage indicator based on the provided NFET leakage current; and
the PFET leakage sensor is further comprised of a PFET ring oscillator circuit comprising a plurality of second buffer circuits coupled together in a ring oscillator, each of the plurality of second buffer circuits configured to be activated by the PFET leakage current indicative of the leakage current of the at least one PFET from the at least one deactivated PFET, the PFET ring oscillator circuit configured to update the PFET leakage indicator based on the provided PFET leakage current.

### Claim 6 (depends on 1)

The leakage-aware activation control circuit of claim 1, wherein:
the NFET leakage circuit further comprises an NFET leakage frequency counter configured to store an NFET leakage frequency count;
the NFET leakage circuit configured to control the NFET leakage frequency counter to update the NFET leakage frequency count as a function of the determined leakage current of the at least one NFET; and
the PFET leakage circuit further comprises a PFET leakage frequency counter configured to store a PFET leakage frequency count;
the PFET leakage circuit configured to control the PFET leakage frequency counter to update the PFET leakage frequency count as a function of the determined leakage current of the at least one PFET.

### Claim 7 (depends on 1)

The leakage-aware activation control circuit of claim 1, wherein:
the comparator circuit is configured to generate the FET leakage signal comprising an FET leakage control signal based on the comparison of the NFET leakage indicator to the PFET leakage indicator; and
the control signal generator is configured to adaptively generate the at least one control signal comprising an FET leakage control word based on the FET leakage control signal to control the activation timing of the delayed keeper circuit.

### Claim 8 (depends on 7)

The leakage-aware activation control circuit of claim 7, wherein the comparator circuit comprises:
at least one PFET leakage comparator circuit configured to:
receive the NFET leakage indicator and the PFET leakage indicator;
compare the NFET leakage indicator to the PFET leakage indicator; and
control the FET leakage control signal to indicate whether the leakage current of the at least one PFET exceeds the leakage current of the at least one NFET, based on the comparison of the NFET leakage indicator to the PFET leakage indicator; and
at least one NFET leakage comparator circuit configured to:
receive the NFET leakage indicator and the PFET leakage indicator;
compare the NFET leakage indicator to the PFET leakage indicator; and
control the FET leakage control signal to indicate whether the leakage current of the at least one NFET exceeds the leakage current of the at least one PFET, based on the comparison of the NFET leakage indicator to the PFET leakage indicator.

### Claim 9 (depends on 8)

The leakage-aware activation control circuit of claim 8, wherein the comparator circuit further comprises:
at least one PFET slow leakage comparator circuit configured to:
receive the PFET leakage indicator;
receive a predefined PFET slow leakage indicator indicative of a PFET slow leakage limit;
compare the predefined PFET leakage indicator to the predefined PFET slow leakage indicator; and
control the FET leakage control signal to indicate a PFET slow leakage current if the leakage current of the at least one PFET is less than the PFET slow leakage limit, based on the comparison of the PFET leakage indicator to the predefined PFET slow leakage indicator; and
at least one NFET slow leakage comparator circuit configured to:
receive the NFET leakage indicator;
receive a predefined NFET slow leakage indicator indicative of an NFET slow leakage limit;
compare the predefined NFET leakage indicator to the predefined NFET slow leakage indicator; and
control the FET leakage control signal to indicate an NFET slow leakage current if the leakage current of the at least one NFET is less than the NFET slow leakage limit, based on the comparison of the NFET leakage indicator to the predefined NFET slow leakage indicator.

### Claim 10 (depends on 8)

The leakage-aware activation control circuit of claim 8, wherein the comparator circuit further comprises:
at least one PFET fast leakage comparator circuit configured to:
receive the PFET leakage indicator;
receive a predefined PFET fast leakage indicator indicative of a PFET fast leakage limit;
compare the PFET leakage indicator to the predefined PFET fast leakage indicator; and
control the FET leakage control signal to indicate a PFET fast leakage current if the leakage current of the at least one PFET is greater than the PFET fast leakage limit, based on the comparison of the PFET leakage indicator to the predefined PFET fast leakage indicator; and
at least one NFET fast leakage comparator circuit configured to:
receive the NFET leakage indicator;
receive a predefined NFET fast leakage indicator indicative of an NFET fast leakage limit;
compare the NFET leakage indicator to the predefined NFET fast leakage indicator; and
control the FET leakage control signal to indicate an NFET fast leakage current if the leakage current of the at least one NFET is greater than the NFET fast leakage limit, based on the comparison of the NFET leakage indicator to the predefined NFET fast leakage indicator.

### Claim 11 (depends on 7)

The leakage-aware activation control circuit of claim 7, wherein the control signal generator comprises a decoder circuit configured to decode the FET leakage control signal into the FET leakage control word to control the activation timing of the delayed keeper circuit.

### Claim 12 (depends on 1)

The leakage-aware activation control circuit of claim 1, wherein the control signal generator is configured to adaptively generate the at least one control signal based on controlling timing of a pulse width of a pulse generated by a pulse generator configured to control the activation timing of the delayed keeper circuit, based on the comparison of the NFET leakage indicator to the PFET leakage indicator.

### Claim 13 (depends on 1)

The leakage-aware activation control circuit of claim 1 integrated into a system-on-a-chip (SoC).

### Claim 14 (depends on 1)

The leakage-aware activation control circuit of claim 1 integrated into a device selected from the group consisting of: a set top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a mobile phone; a cellular phone; a smart phone; a tablet; a phablet; a server; a computer; a portable computer; a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; and an automobile.

### Claim 15

A leakage-aware activation control circuit for controlling activation of a delayed keeper circuit in a dynamic read circuit for a memory bit cell, comprising:
means for providing an N-type Field-Effect Transistor (NFET) leakage indicator indicating leakage current of at least one NFET in a dynamic read circuit;
means for providing a P-type FET (PFET) leakage indicator indicating leakage current of at least one PFET in the dynamic read circuit;
means for receiving the NFET leakage indicator and the PFET leakage indicator;
means for comparing the NFET leakage indicator to the PFET leakage indicator;
means for generating a FET leakage signal based on the comparison of the NFET leakage indicator to the PFET leakage indicator; and
means for adaptively generating at least one control signal based on the FET leakage signal to control activation timing of a delayed keeper circuit.

### Claim at position 16

16-26. (canceled)

### Claim 27

A memory system, comprising:
a memory bit cell comprising:
a storage circuit configured to store a complement voltage; and
a read port circuit coupled to the storage circuit, the read port circuit configured to generate the complement voltage on a dynamic node in response to a read operation;, p;
a dynamic read circuit, comprising:
the dynamic node;
a delayed keeper circuit configured to be activated in response to a pulse to keep the complement voltage on the dynamic node outside of an evaluation phase, and configured to be deactivated in response to the pulse in response to the evaluation phase of the read operation;
a leakage-aware activation control circuit, comprising:
a leakage circuit configured to generate a FET leakage signal based on a comparison of leakage current of at least one N-type FET (NFET) to leakage current of at least one P-type FET (PFET); and
a control signal generator configured to adaptively generate at least one control signal based on the FET leakage signal to control activation timing of a second delayed keeper circuit; and
a pulse generator configured to generate the pulse having a pulse width based on a control activation timing for activation and deactivation of the second delayed keeper circuit in response to the at least one control signal.

### Claim 28 (depends on 27)

The memory system of claim 27, wherein the read port circuit is comprised of an NFET-based read port circuit, and the delayed keeper circuit is comprised of a PFET-based delayed keeper circuit.

### Claim 29 (depends on 27)

The memory system of claim 27, wherein the read port circuit is comprised of a PFET-based read port circuit, and the delayed keeper circuit is comprised of an NFET-based delayed keeper circuit.

### Claim 30 (depends on 27)

The memory system of claim 27, wherein:
the control signal generator is configured to adaptively generate the at least one control signal comprising a FET leakage control word based on the FET leakage signal to control the activation timing of the second delayed keeper circuit; and
the pulse generator comprises:
a plurality of delay circuits each configured to receive a read clock signal in response to the read operation, each delay circuit among the plurality of delay circuits corresponding to a leakage control setting of the FET leakage control word; and
a selector circuit configured to select the delay circuit among the plurality of delay circuits based on the leakage control setting of the FET leakage control word to control a pulse width of the generated pulse.