# US 2017/0287545 A1 · Semiconductor device having pda function

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- Number: US 2017/0287545 A1
- Document ID: US20170287545A1
- Status: Published application
- Kind: A1
- Application number: 15/624,511
- Filed: 2017-06-15
- Published: 2017-10-05
- Earliest claimed: 2011-09-28
- Assignees: Longitude Semiconductor S.a.r.l.
- Applicants: Longitude Semiconductor S.a.r.l.
- Inventors: Chikara Kondo
- Web page: https://patentgrep.com/patent/US20170287545A1

## CPC

- G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers
- G06F 13/161: {with latency improvement}
- G11C 7/1045: {Read-write mode select circuits}
- G11C 7/109: {Control signal input circuits}
- G11C 7/1093: {Input synchronization}
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 11/4063: Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C 11/4072: Circuits for initialization, powering up or down, clearing memory or presetting
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 11/4087: {Address decoders, e.g. bit - or word line decoders; Multiple line decoders}
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 2207/2272: Latency related aspects
- Y02D 10/00: Energy efficient computing, e.g. low power processors, power management or thermal management
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02D: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE

## Abstract

A method for writing a mode register in a semiconductor device, the method includes receiving a mode register command and a mode signal; generating a first mode register setting signal; delaying the first mode register setting signal in a first latency shifter to provide a second mode register setting signal; receiving a data signal in synchronization with the second mode register setting signal; and writing the mode signal to the mode register only if the received data signal has a first logic level.

## Claims

### Claim 1

A method for controlling a plurality of memory devices comprising:
supplying a first enable signal having a first logic level to a first memory device of a plurality of memory devices, the first enable signal being supplied with a predetermined latency after supplying a mode register command and a mode signal; and
supplying a second enable signal having a second logic level to a second memory device of the plurality of memory devices, the second signal being supplied with the predetermined latency after supplying the mode register command and the mode signal;
wherein the mode register command is decoded and delayed by a latency shifter in each of the plurality of memory devices, the mode signal is written to a first mode register of the first memory device, and the mode signal is not written to a first mode register of the second memory device.