# US 2017/0287544 A1 · Refresh circuitry > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 2017/0287544 A1 - Document ID: US20170287544A1 - Status: Published application - Kind: A1 - Application number: 15/614,983 - Filed: 2017-06-06 - Published: 2017-10-05 - Earliest claimed: 2016-04-05 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Richard N. Hedden - Web page: https://patentgrep.com/patent/US20170287544A1 ## CPC - G11C 11/406: Management or control of the refreshing or charge-regeneration cycles - G11C 11/40622: {Partial refresh of memory arrays} - G11C 29/76: {using address translation or modifications} - G11C 29/783: {with refresh of replacement cells, e.g. in DRAMs} - G11C 11/4078: Safety or protection circuits, e.g. for preventing inadvertent or unauthorised reading or writing; Status cells; Test cells (protection of memory contents during checking or testing G11C29/52) - G11C 11/408: Address circuits - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract The present disclosure includes apparatuses and methods related to refresh circuitry. An example apparatus can include a memory array including a main portion and a redundant portion. The apparatus can include refresh circuitry configured to, responsive to a determination of a hammering event, refresh at least a portion of the redundant portion. ## Claims ### Claim at position 1 -21. (canceled) ### Claim 21 An apparatus comprising: a memory array comprising: a main portion; and a redundant portion; and refresh circuitry configured to, responsive to a determination of a hammering event, refresh at least a portion of the redundant portion. ### Claim 22 (depends on 21) The apparatus of claim 21, wherein the refresh circuitry is configured to refresh the at least a portion of the redundant portion independent of the at least a portion being associated with cells that experienced the hammering event. ### Claim 23 (depends on 21) The apparatus of claim 21, wherein the determination of the hammering event includes a determination that a group of memory cells has been accessed at a threshold rate. ### Claim 24 (depends on 21) The apparatus of claim 21, wherein the determination of the hammering event includes a determination that a group of memory cells has been accessed a threshold number of times within a refresh window. ### Claim 25 (depends on 21) The apparatus of claim 21, wherein the portion of the redundant portion comprises at least two groups of memory cells coupled to different access lines. ### Claim 26 (depends on 21) The apparatus of claim 21, wherein: the hammering event is associated with a hammered access line coupling a group of memory cells in the redundant portion; the hammered access line corresponds to a particular remapped access line of the main portion; and at least one access line adjacent to the particular remapped access line is not refreshed responsive to the determination of the hammering event. ### Claim 27 (depends on 21) The apparatus of claim 21, wherein the apparatus includes a controller coupled to the refresh circuitry and configured to determine hammering events. ### Claim 28 An apparatus, comprising: a memory array, wherein the memory array comprises: a main portion; and a redundant portion; refresh circuitry coupled to the memory array to: refresh at least a portion of the redundant portion in response to a determination of a hammering event; and refrain from refreshing a portion of the main portion in response to the determination of the hammering event; wherein the portion of the main portion is a first group of memory cells adjacent to a second group of memory cells of the main portion. ### Claim 29 (depends on 28) The apparatus of claim 28, wherein a physical address of the second group of memory cells is mapped to the redundant portion. ### Claim 30 (depends on 29) The apparatus of claim 29, wherein the at least a portion of the redundant portion is refreshed independent of which group of cells in the main portion the at least a portion is mapped to. ### Claim 31 (depends on 28) The apparatus of claim 28, wherein the determined hammering event occurs on a group of cells coupled to an access line of the redundant portion. ### Claim 32 (depends on 28) The apparatus of claim 28, comprising a controller configured to, responsive to an attempt to access the group of memory cells in the main portion whose physical address has been mapped to the redundant portion, access a portion of the redundant portion to which the physical address is mapped. ### Claim 33 (depends on 32) The apparatus of claim 32, wherein the hammering event comprises the controller accessing the portion of the redundant portion greater than a threshold number of times in a particular amount of time. ### Claim 34 A method, comprising: accessing a first group of redundant memory cells of a memory array at a particular rate; and refreshing, using hammer refresh circuitry, the first group of redundant memory cells and a second group of redundant memory cells in response to the first group being accessed at the particular rate, wherein the refreshing includes not refreshing at least a third group of redundant memory cells. ### Claim 35 (depends on 34) The method of claim 34, comprising refreshing main memory cells of the memory array at a rate different than the particular rate. ### Claim 36 (depends on 34) The method of claim 34, wherein refreshing the first group and the second group of redundant memory cells comprises refreshing all redundant memory cells of the memory array. ### Claim 37 (depends on 34) The method of claim 34, wherein the first group of redundant memory cells are accessed in response to a corresponding group of main memory cells determined to be defective. ### Claim 38 (depends on 34) The method of claim 34, wherein the second group of redundant memory cells are refreshed independent of whether the second group of redundant memory cells and a group of memory cells adjacent to the second group of redundant memory cells are accessed. ### Claim 39 (depends on 34) The method of claim 34, wherein refreshing the first group of redundant memory cells and the second group of redundant memory cells comprises refreshing the first and second groups of redundant memory cells by using counter circuitry to cycle through addresses associated with each of the rows of the redundant array. ### Claim 40 (depends on 34) The method of claim 34, comprising determining the particular number of accesses.