# US 2017/0287539 A1 · Timing control for unmatched signal receiver

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- Number: US 2017/0287539 A1
- Document ID: US20170287539A1
- Status: Published application
- Kind: A1
- Application number: 15/490,860
- Filed: 2017-04-18
- Published: 2017-10-05
- Earliest claimed: 2013-07-01
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Christopher P. MOZAK
- Web page: https://patentgrep.com/patent/US20170287539A1

## CPC

- G06F 1/04: Generating or distributing clock signals or signals derived directly therefrom
- G06F 13/4291: {using a clocked protocol}
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 27/02: Sample-and-hold arrangements (G11C27/04 takes precedence)
- H03L 7/00: Automatic control of frequency or phase; Synchronisation
- H04L 7/0008: {Synchronisation information channels, e.g. clock distribution lines}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03L: AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES (generation of oscillations H03B)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

A device with an I/O interface includes a replica clock distribution path matched to a clock distribution path of an unmatched receiver circuit. The device can monitor changes in delay in the replica path, and adjust delay in the real clock distribution path in response to the delay changes detected in the replica path. The receiver circuit includes a data path and a clock distribution network in an unmatched configuration. A ring oscillator circuit includes a replica clock distribution network matched to the real clock distribution network. Thus, delay changes detected for the replica clock distribution network indicates a change in delay in the real clock distribution network, which can be compensated accordingly.

## Claims

### Claim at position 1

1-20. (canceled)

### Claim 21

A memory device comprising:
a receiver circuit to receive a data (DQ) signal and a data strobe (DQS) signal;
circuitry including a ring oscillator and a copy of a data strobe (DQS) clock tree, the circuitry to:
start the ring oscillator in response to a command from a memory controller,
count a number of times the DQS signal propagates through the copy of the DQS clock tree, and
stop the ring oscillator in response to a second command from the memory controller; and
one or more registers to store a count from the ring oscillator.

### Claim 22 (depends on 21)

The memory device of claim 21, wherein the circuitry to start the ring oscillator in response to the command comprises:
circuitry to start the ring oscillator in response to a command to start oscillation.

### Claim 23 (depends on 21)

The memory device of claim 21, wherein the circuitry to stop the ring oscillator in response to the second command comprises:
circuitry to stop the ring oscillator in response to a command to stop oscillation.

### Claim 24 (depends on 21)

The memory device of claim 21, wherein the circuitry is to:
store the count in the one or more registers at least in part in response to receipt of the second command.

### Claim 25 (depends on 21)

The memory device of claim 21, wherein the receiver circuit is to sample a (data) DQ voltage of the DQ signal at a DQ pad.

### Claim 26 (depends on 21)

The memory device of claim 21, wherein the DQS clock tree comprises a clock distribution network.

### Claim 27 (depends on 21)

The memory device of claim 21, wherein the DQS clock tree comprises a binary tree.

### Claim 28 (depends on 27)

The memory device of claim 27, wherein the binary tree comprises an H-tree.

### Claim 29 (depends on 21)

The memory device of claim 21, wherein the copy of the DQS clock tree comprises a circuit equivalent to the DQS clock tree.

### Claim 30 (depends on 21)

The memory device of claim 21, wherein a data (DQ) path via which the DQ signal is to be received comprises an amplifier that is unmatched to an amplifier of the DQS clock tree.

### Claim 31 (depends on 30)

The memory device of claim 30, wherein the copy of the DQS clock tree comprises an amplifier that is matched to the amplifier of the DQS clock tree.

### Claim 32 (depends on 21)

The memory device of claim 21, wherein the receiver circuit is to further receive command signals, including:
to receive one or more mode register read (MRR) commands to read the count from the ring oscillator from the one or mode registers.

### Claim 33

A memory device comprising:
a receiver circuit to receive a data (DQ) signal and to receive a clock signal;
circuitry including a ring oscillator and a copy of a clock tree, the circuitry to:
start the ring oscillator in response to a command from a memory controller,
count a number of times the clock signal propagates through the copy of the clock tree, and
stop the ring oscillator in response to a second command from the memory controller; and
one or more registers to store a count from the ring oscillator.

### Claim 34 (depends on 33)

The memory device of claim 33, wherein the clock signal comprises a data strobe (DQS) signal, and the clock tree comprises a DQS clock tree.

### Claim 35 (depends on 33)

The memory device of claim 33, wherein the circuitry to start the ring oscillator in response to the command comprises:
circuitry to start the ring oscillator in response to a command to start oscillation.

### Claim 36 (depends on 33)

The memory device of claim 33, wherein the circuitry to stop the ring oscillator in response to the second command comprises:
circuitry to stop the ring oscillator in response to a command to stop oscillation.

### Claim 37 (depends on 33)

The memory device of claim 33, wherein the circuitry is to:
store the count in the one or more registers at least in part in response to receipt of the second command.

### Claim 38 (depends on 33)

The memory device of claim 33, wherein the receiver circuit is to sample a (data) DQ voltage of the DQ signal at a DQ pad.

### Claim 39 (depends on 33)

The memory device of claim 33, wherein the clock tree comprises a clock distribution tree.

### Claim 40 (depends on 33)

The memory device of claim 33, wherein the clock tree comprises a binary tree.

### Claim 41 (depends on 40)

The memory device of claim 40, wherein the binary tree comprises an H-tree.

### Claim 42 (depends on 33)

The memory device of claim 33, wherein the copy of the clock tree comprises a circuit equivalent to the clock tree.

### Claim 43 (depends on 33)

The memory device of claim 33, wherein a DQ path via which the DQ signal is to be received comprises an amplifier that is unmatched to an amplifier of the clock tree.

### Claim 44 (depends on 43)

The memory device of claim 43, wherein the copy of the clock tree comprises an amplifier that is matched to the amplifier of the clock tree.

### Claim 45 (depends on 33)

The memory device of claim 33, wherein the receiver circuit is to further receive a command signal, including:
to receive one or more mode register read (MRR) commands to read the count from the ring oscillator from the one or mode registers.

### Claim 46

A memory controller comprising:
a transmitter circuit to:
transmit a command to a memory device to start a data strobe (DQS) ring oscillator,
transmit a second command to the memory device to stop the DQS ring oscillator, and
transmit one or more commands to the memory device to read one or more mode registers, the one or more mode registers to store a result from a DQS ring oscillator counter; and
circuitry to delay a data (DQ) signal relative to a data strobe (DQS) signal to the memory device based on the count from the DQS ring oscillator.

### Claim 47 (depends on 46)

The memory controller of claim 46, wherein the circuitry is to:
compare the count to a previous count and delay the DQ signal based on the comparison.

### Claim 48 (depends on 46)

The memory controller of claim 46, wherein the circuitry is to:
delay the DQ signal via an adjustment in operation of the transmitter circuit.

### Claim 49 (depends on 46)

The memory controller of claim 46, wherein:
the circuitry is to determine a duration to run the DQS ring oscillator; and
the transmitter circuit is to transmit the second command to stop the DQS ring oscillator after a delay in accordance with the duration.

### Claim 50

A memory controller comprising:
a transmitter circuit to:
transmit a command to a memory device to start a ring oscillator,
transmit a second command to the memory device to stop the ring oscillator, and
transmit one or more commands to the memory device to read one or more mode registers, the one or more mode registers to store a result of an oscillator counter; and
circuitry to delay a data (DQ) signal relative to a clock signal to the memory device based on the count from the ring oscillator.

### Claim 51 (depends on 50)

The memory controller of claim 50, wherein the clock signal comprises a data strobe (DQS) signal.

### Claim 52 (depends on 50)

The memory controller of claim 50, wherein the circuitry is to:
compare the count to a previous count and delay the DQ signal based on the comparison.

### Claim 53 (depends on 50)

The memory controller of claim 50, wherein the circuitry is to:
delay the DQ signal via an adjustment in operation of the transmitter circuit.

### Claim 54 (depends on 50)

The memory controller of claim 50, wherein:
the circuitry is to determine a duration to run the ring oscillator; and
the transmitter circuit is to transmit the second command to stop the ring oscillator after a delay in accordance with the duration.